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1. 发明申请

US20080107168A1 Advanced Digital Receiver 有权
标题翻译：高级数字接收机
公开(公告)号：US20080107168A1
公开(公告)日：2008-05-08
申请号：US11547816
申请日：2005-04-08
申请人： Jingsong Xia , Shidong Chen , Richard W. Citta , Gopalan Krishnamurthy , Scott M. Lopresto , David A. Willming , Xiaojun Yang , Jilian Zhu
发明人： Jingsong Xia , Shidong Chen , Richard W. Citta , Gopalan Krishnamurthy , Scott M. Lopresto , David A. Willming , Xiaojun Yang , Jilian Zhu
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L1/006 , H04L7/0062 , H04L7/042 , H04L25/0212
摘要： A digital receiver for processing a signal received from a channel includes a digital demodulator and an equalizer coupled to the digital demodulator. The equalizer includes a feedforward filter and a decision feedback equalizer (DFE), wherein the feedforward filter includes a plurality of feedforward filter taps. Coefficients are associated with the plurality of feedforward filter taps and the values of all of the coefficients associated with the plurality of feedforward filter taps are dynamically determined.
摘要翻译：用于处理从信道接收的信号的数字接收机包括耦合到数字解调器的数字解调器和均衡器。均衡器包括前馈滤波器和判决反馈均衡器（DFE），其中前馈滤波器包括多个前馈滤波器抽头。系数与多个前馈滤波器抽头相关联，并且动态地确定与多个前馈滤波器抽头相关联的所有系数的值。

2. 发明授权

US07995648B2 Advanced digital receiver 有权
标题翻译：高级数字接收机
公开(公告)号：US07995648B2
公开(公告)日：2011-08-09
申请号：US11547816
申请日：2005-04-08
申请人： Jingsong Xia , Shidong Chen , Richard W. Citta , Gopalan Krishnamurthy , Scott M. Lopresto , David A. Willming , Xiaojun Yang , Jilian Zhu
发明人： Jingsong Xia , Shidong Chen , Richard W. Citta , Gopalan Krishnamurthy , Scott M. Lopresto , David A. Willming , Xiaojun Yang , Jilian Zhu
IPC分类号： H04B1/10 , H04L1/00
CPC分类号： H04L25/03057 , H04L1/006 , H04L7/0062 , H04L7/042 , H04L25/0212
摘要： A digital receiver for processing a signal received from a channel includes a digital demodulator and an equalizer coupled to the digital demodulator. The equalizer includes a feedforward filter and a decision feedback equalizer (DFE), wherein the feedforward filter includes a plurality of feedforward filter taps. Coefficients are associated with the plurality of feedforward filter taps and the values of all of the coefficients associated with the plurality of feedforward filter taps are dynamically determined.
摘要翻译：用于处理从信道接收的信号的数字接收机包括耦合到数字解调器的数字解调器和均衡器。均衡器包括前馈滤波器和判决反馈均衡器（DFE），其中前馈滤波器包括多个前馈滤波器抽头。系数与多个前馈滤波器抽头相关联，并且动态地确定与多个前馈滤波器抽头相关联的所有系数的值。

3. 发明授权

US08483317B2 Apparatus for and method of controlling sampling frequency and sampling phase of a sampling device 有权
标题翻译：用于控制取样装置的采样频率和采样相位的装置和方法
公开(公告)号：US08483317B2
公开(公告)日：2013-07-09
申请号：US11547819
申请日：2005-04-08
申请人： Jilian Zhu , Richard W. Citta , Scott M. Lopresto , David A. Willming , Shidong Chen
发明人： Jilian Zhu , Richard W. Citta , Scott M. Lopresto , David A. Willming , Shidong Chen
IPC分类号： H04B1/10
CPC分类号： H04L25/03057 , H04L7/0062 , H04L25/0212 , H04L2025/0342 , H04L2025/0349
摘要： A method of controlling sampling frequency and sampling phase of a sampling device from a value generated by an equalizer coupled to the sampling device includes the steps of generating a complex representation of the value developed by the equalizer and generating a representation of a decision from an output of the equalizer. The complex representation and the decision representation are correlated to obtain a sampling error estimate. The sampling error estimate is used to adjust the sampling frequency and sampling phase of the sampling device.
摘要翻译：根据耦合到采样装置的均衡器产生的值来控制采样装置的采样频率和采样相位的方法包括以下步骤：产生由均衡器开发的值的复数表示，并从输出端生成决策的表示的均衡器。复数表示和决策表示相关，以获得抽样误差估计。采样误差估计用于调整采样设备的采样频率和采样相位。

4. 发明授权

US07545888B2 Apparatus for and method of controlling a digital demodulator coupled to an equalizer 有权
标题翻译：用于控制耦合到均衡器的数字解调器的装置和方法
公开(公告)号：US07545888B2
公开(公告)日：2009-06-09
申请号：US11547818
申请日：2005-04-08
申请人： Jilian Zhu , Richard W. Citta , Scott M. Lopresto , Shidong Chen
发明人： Jilian Zhu , Richard W. Citta , Scott M. Lopresto , Shidong Chen
IPC分类号： H04L27/00 , H04L27/06
CPC分类号： H04L25/03057 , H04L7/0062 , H04L25/0212 , H04L2025/0342 , H04L2025/0349
摘要： A method of controlling a digital demodulator (922) coupled to an equalizer (930) includes the steps of generating an equalizer value (930A), filtering (944) the equalizer value (930A) to obtain a post filter output, subtracting the equalizer output signal (930C) from the decoded data (930D) and generating an error value (924A). The post filter output is correlated (948) with the error value (924A) to obtain a correlated value (74A). A control signal is developed from the correlated value and is used to adjust the digital demodulator (922).
摘要翻译：一种控制耦合到均衡器（930）的数字解调器（922）的方法包括以下步骤：产生均衡器值（930A），滤波（944）均衡器值（930A）以获得后置滤波器输出，减去均衡器输出信号（930C）并产生误差值（924A）。后滤波器输出与误差值（924A）相关（948）以获得相关值（74A）。根据相关值产生控制信号，用于调整数字解调器（922）。

5. 发明授权

US07130344B2 Adaptive equalizer having a variable step size influenced by output from a trellis decoder 有权
公开(公告)号：US07130344B2
公开(公告)日：2006-10-31
申请号：US10701047
申请日：2003-11-04
申请人： Jingsong Xia , Richard W. Citta , Scott M. LoPresto , Wenjun Zhang , Hangbin Song
发明人： Jingsong Xia , Richard W. Citta , Scott M. LoPresto , Wenjun Zhang , Hangbin Song
IPC分类号： H03H7/40
CPC分类号： H04L1/006 , H04L1/0054 , H04L1/1671 , H04L25/03057 , H04L2025/0349 , H04L2025/03617 , H04L2025/03624 , H04L2025/03687
摘要： An adaptive equalizer comprises a decision device; a decision feedback equalizer coupled to the decision device; an FIR filter coupled to the decision device; and a trellis decoder coupled to the decision device, adapted to provide a reliability output and a decoded output. An error signal is generated by subtracting an output of the decision feedback equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.

6. 发明授权

US06995617B2 Data-directed frequency-and-phase lock loop 有权
公开(公告)号：US06995617B2
公开(公告)日：2006-02-07
申请号：US10404511
申请日：2003-04-01
申请人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia , Wenjun Zhang
发明人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia , Wenjun Zhang
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/093 , H04L27/38 , H04L2027/0057
摘要： A data-directed frequency-and-phase lock loop for an offset-QAM modulated signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is phase-shifted by a second multiplier, then convolved by a third multiplier. The output of the third multiplier is split, with each portion being passed through a frequency-shift multiplier and a frequency-and-phase lock loop. The output of the two frequency-and-phase lock loops is summed and returned to the VCO to complete the feedback loop.

7. 发明授权

US07305026B1 Multipath ghost eliminating equalizer with optimum noise enhancement 有权
标题翻译：多路径消除均衡器，具有最佳的噪声增强
公开(公告)号：US07305026B1
公开(公告)日：2007-12-04
申请号：US09545597
申请日：2000-04-07
申请人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia
发明人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03159
摘要： An equalizer for processing blocks of data includes n−1 data shifters, n finite filters, an adder, and a controller. Each of the n−1 data shifters shifts the blocks of data. One of the n finite filters applies a corresponding set of finite filter coefficients to the blocks of data, and each of the other n−1 finite filters applies a set of finite filter coefficients to a corresponding output of the n−1 data shifters. Ghosts of the blocks of data are not eliminated as a result of the application of the n sets of finite filter coefficients corresponding to the n finite filters, and n>2. The adder is arranged to add outputs from the n finite filters. The controller is arranged to control the sets of finite filter coefficients corresponding to the n finite filters so that the addition performed by the adder substantially eliminates the ghosts.
摘要翻译：用于处理数据块的均衡器包括n-1个数据移位器，n个有限滤波器，加法器和控制器。每个n-1个数据移位器移动数据块。 n个有限滤波器中的一个将有限滤波器系数的一组应用于数据块，并且其他n-1个有限滤波器中的每一个将一组有限滤波器系数应用于n-1个数据移位器的相应输出。由于应用与n个有限滤波器相对应的n组有限滤波器系数，并且n> 2，所以数据块的Ghost不被消除。加法器被布置成从n个有限滤波器加上输出。控制器被设置为控制与n个有限滤波器相对应的有限滤波器系数的集合，使得由加法器执行的加法器基本上消除了重影。

8. 发明授权

US07072392B2 Equalizer for time domain signal processing 有权
公开(公告)号：US07072392B2
公开(公告)日：2006-07-04
申请号：US10007999
申请日：2001-11-13
申请人： Jingsong Xia , Richard W. Citta , Scott M. LoPresto , Wenjun Zhang
发明人： Jingsong Xia , Richard W. Citta , Scott M. LoPresto , Wenjun Zhang
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L2025/0349
摘要： A digital equalizer comprises a matched filter that, in conjunction with an FIR filter, assures a single peak with substantially greater energy than other peaks caused by ghosts, thereby permitting synchronization even with multiple, arbitrarily strong ghosts caused by strong multipathing, multiple transmitters, or both.

9. 发明授权

US06829297B2 Adaptive equalizer having a variable step size influenced by output from a trellis decoder 失效
公开(公告)号：US06829297B2
公开(公告)日：2004-12-07
申请号：US09875720
申请日：2001-06-06
申请人： Jingsong Xia , Richard W. Citta , Scott M. LoPresto , Wenjun Zhang , Hangbin Song
发明人： Jingsong Xia , Richard W. Citta , Scott M. LoPresto , Wenjun Zhang , Hangbin Song
IPC分类号： H03K5159
CPC分类号： H04L1/006 , H04L1/0054 , H04L1/1671 , H04L25/03057 , H04L2025/0349 , H04L2025/03617 , H04L2025/03624 , H04L2025/03687
摘要： An adaptive equalizer comprises a decision device; a decision feedback equalizer coupled to the decision device; an FIR filter coupled to the decision device; and a trellis decoder coupled to the decision device, adapted to provide a reliability output and a decoded output. An error signal is generated by subtracting an output of the decision feedback equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.

10. 发明授权

US06731682B1 Multipath ghost eliminating equalizer with optimum noise enhancement 有权
标题翻译：多路径消除均衡器，具有最佳的噪声增强
公开(公告)号：US06731682B1
公开(公告)日：2004-05-04
申请号：US09545716
申请日：2000-04-07
申请人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia
发明人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia
IPC分类号： H03H730
CPC分类号： H04L25/03159 , H04L2025/03414 , H04L2025/03522 , H04L2025/03617
摘要： An equalizer applies a window function to input blocks of data. A first finite filter multiplies each of the windowed input blocks of data with a first set of finite filter coefficients to provide respective first adjusted output blocks of data. This multiplication does not result in a full solution to ghosts. A second finite filter multiplies each of the windowed input blocks of data with a second set of finite filter coefficients to provide respective second adjusted output blocks of data. This multiplication also does not result in a full solution to ghosts. An adder performs an addition based upon corresponding ones of the first and second adjusted output blocks of data. A controller controls the window function and the first and second sets of equalizer coefficients so that, as a result of the addition, a substantially full solution to ghosts is obtained.
摘要翻译：均衡器将窗口函数应用于输入数据块。第一有限滤波器将每个窗口输入的数据块与第一组有限滤波器系数相乘以提供相应的第一调整的数据输出块。这种乘法不会导致对幽灵的完整解决。第二有限滤波器将每个窗口输入的数据块与第二组有限滤波器系数相乘，以提供相应的第二调整的数据输出块。这种乘法也不能完全解决鬼魂。加法器基于第一和第二调整的数据输出块中的对应的一个执行相加。控制器控制窗口功能和第一和第二组均衡器系数，使得作为添加的结果，获得了对重影的基本上完全的解决方案。

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