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1. 发明授权

US08362582B2 Semiconductor nanostructures, semiconductor devices, and methods of making same 有权
标题翻译：半导体纳米结构，半导体器件及其制造方法
公开(公告)号：US08362582B2
公开(公告)日：2013-01-29
申请号：US13041754
申请日：2011-03-07
申请人： Joerg Appenzeller , Supratik Guha , Emanuel Tutuc
发明人： Joerg Appenzeller , Supratik Guha , Emanuel Tutuc
IPC分类号： H01L31/058
CPC分类号： H01L21/30604 , B82Y10/00 , H01L21/02603 , H01L29/0665 , H01L29/0673 , H01L29/068 , H01L29/1041 , H01L29/125 , H01L29/42392 , H01L29/66439 , H01L29/78696
摘要： A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.
摘要翻译：提供了一种半导体结构，其包括沿纵向轴线布置的多个部分。优选地，半导体结构包括位于中间部分的相对端的中间部分和两个端子部分。具有第一掺杂剂浓度的半导体芯片优选地沿着纵向轴线延伸通过中间部分和两个端子部分。具有第二较高掺杂剂浓度的半导体壳体优选地环绕半导体结构的两个端子部分但不在中间部分处的半导体芯体的一部分。特别优选的是，半导体结构是具有不大于100nm的横截面尺寸的纳米结构。

2. 发明申请

US20120142158A1 Self-Aligned Nanotube Field Effect Transistor and Method of Fabricating Same 有权
标题翻译：自对准纳米管场效应晶体管及其制造方法
公开(公告)号：US20120142158A1
公开(公告)日：2012-06-07
申请号：US13368901
申请日：2012-02-08
申请人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
发明人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L51/0516 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L51/0545 , Y10S977/842 , Y10S977/938 , Y10S977/94
摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
摘要翻译：自对准碳纳米管场效应晶体管半导体器件分别包括沉积在基板上的碳纳米管，分别形成在碳纳米管的第一端和第二端的源极和漏极，以及基本上形成的栅极碳纳米管的一部分，通过电介质膜与碳纳米管分离。

3. 发明申请

US20110263101A1 CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT 失效
标题翻译：基于碳纳米管的集成半导体电路
公开(公告)号：US20110263101A1
公开(公告)日：2011-10-27
申请号：US13170525
申请日：2011-06-28
申请人： Joerg Appenzeller , AJ Kleinosowski , Edward J. Nowak , Richard Q. Williams
发明人： Joerg Appenzeller , AJ Kleinosowski , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/20 , B82Y40/00
CPC分类号： H01L51/0541 , B82Y10/00 , H01L27/11 , H01L27/1104 , H01L27/283 , H01L51/0048 , H01L51/0558 , Y10S977/742 , Y10S977/75 , Y10S977/751 , Y10S977/752
摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.
摘要翻译：在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过电介质层对两个器件区域之间的电介质层进行电偏置碳纳米管。碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

4. 发明授权

US07948050B2 Core-shell nanowire transistor 有权
标题翻译：核壳纳米线晶体管
公开(公告)号：US07948050B2
公开(公告)日：2011-05-24
申请号：US11622358
申请日：2007-01-11
申请人： Joerg Appenzeller , Supratik Guha , Emanuel Tutuc
发明人： Joerg Appenzeller , Supratik Guha , Emanuel Tutuc
IPC分类号： H01L31/06
CPC分类号： H01L21/30604 , B82Y10/00 , H01L21/02603 , H01L29/0665 , H01L29/0673 , H01L29/068 , H01L29/1041 , H01L29/125 , H01L29/42392 , H01L29/66439 , H01L29/78696
摘要： A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.
摘要翻译：提供了一种半导体结构，其包括沿纵向轴线布置的多个部分。优选地，半导体结构包括位于中间部分的相对端的中间部分和两个端子部分。具有第一掺杂剂浓度的半导体芯片优选地沿着纵向轴线延伸通过中间部分和两个端子部分。具有第二较高掺杂剂浓度的半导体壳体优选地环绕半导体结构的两个端子部分但不在中间部分处的半导体芯体的一部分。特别优选的是，半导体结构是具有不大于100nm的横截面尺寸的纳米结构。

5. 发明申请

US20100295025A1 CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT 有权
标题翻译：基于碳纳米管的集成半导体电路
公开(公告)号：US20100295025A1
公开(公告)日：2010-11-25
申请号：US12850259
申请日：2010-08-04
申请人： Joerg Appenzeller , AJ Kleinosowski , Edward J. Nowak , Richard Q. Williams
发明人： Joerg Appenzeller , AJ Kleinosowski , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L51/0541 , B82Y10/00 , H01L27/11 , H01L27/1104 , H01L27/283 , H01L51/0048 , H01L51/0558 , Y10S977/742 , Y10S977/75 , Y10S977/751 , Y10S977/752
摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.
摘要翻译：在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过介电层在两个器件区域之间电气偏置区域碳纳米管。碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

6. 发明申请

US20050274992A1 Method of fabricating a tunneling nanotube field effect transistor 有权
标题翻译：制造隧道纳米管场效应晶体管的方法
公开(公告)号：US20050274992A1
公开(公告)日：2005-12-15
申请号：US10852891
申请日：2004-05-25
申请人： Joerg Appenzeller , Joachim Knoch
发明人： Joerg Appenzeller , Joachim Knoch
IPC分类号： H01L29/06 , H01L29/739 , H01L29/80 , H01L29/88 , H01L51/00 , H01L51/30
CPC分类号： B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/739 , H01L29/88 , H01L51/0048 , H01L51/0052 , H01L51/0562 , Y10S977/734 , Y10S977/742 , Y10S977/749 , Y10S977/755 , Y10S977/815 , Y10S977/855 , Y10S977/938
摘要： A method of fabricating a tunneling nanotube field effect transistor includes forming in a nanotube an n-doped region and a p-doped region which are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a gate dielectric layer deposited on at least a portion of the channel region of the transistor.
摘要翻译：制造隧道状纳米管场效应晶体管的方法包括在纳米管中形成由晶体管的未掺杂沟道区分离的n掺杂区域和p掺杂区域。为掺杂区域提供电触点，以及形成在沉积在晶体管的沟道区域的至少一部分上的栅极电介质层上的栅电极。

7. 发明授权

US08138491B2 Self-aligned nanotube field effect transistor 有权
标题翻译：自对准纳米管场效应晶体管
公开(公告)号：US08138491B2
公开(公告)日：2012-03-20
申请号：US12544436
申请日：2009-08-20
申请人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
发明人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
IPC分类号： H01L29/76 , H01L29/04 , H01L29/94
CPC分类号： H01L51/0516 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L51/0545 , Y10S977/842 , Y10S977/938 , Y10S977/94
摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
摘要翻译：自对准碳纳米管场效应晶体管半导体器件分别包括沉积在基板上的碳纳米管，分别形成在碳纳米管的第一端和第二端的源极和漏极，以及基本上形成的栅极碳纳米管的一部分，通过电介质膜与碳纳米管分离。

8. 发明授权

US07635856B2 Vertical nanotube field effect transistor 有权
标题翻译：垂直纳米管场效应晶体管
公开(公告)号：US07635856B2
公开(公告)日：2009-12-22
申请号：US11835167
申请日：2007-08-07
申请人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
发明人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
IPC分类号： H01L29/76 , H01L29/06 , H01L29/94
CPC分类号： H01L51/0516 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L51/0545 , Y10S977/842 , Y10S977/938 , Y10S977/94
摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
摘要翻译：自对准碳纳米管场效应晶体管半导体器件分别包括沉积在基板上的碳纳米管，分别形成在碳纳米管的第一端和第二端的源极和漏极，以及基本上形成的栅极碳纳米管的一部分，通过电介质膜与碳纳米管分离。

9. 发明授权

US07482232B2 Method for fabricating a nanotube field effect transistor 失效
标题翻译：纳米管场效应晶体管的制造方法
公开(公告)号：US07482232B2
公开(公告)日：2009-01-27
申请号：US11553331
申请日：2006-10-26
申请人： Joerg Appenzeller , Phaedon Avouris , Yu-Ming Lin
发明人： Joerg Appenzeller , Phaedon Avouris , Yu-Ming Lin
IPC分类号： H01L29/76
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , Y10S977/721
摘要： The method includes forming a 1-10000 nm thick SiO2, HfO2, Al2O3 and/or quartz gate dielectric on an Si back gate. An Al or Mo gate electrode is formed on the gate dielectric. An Al2O3 insulating layer is formed over the gate electrode. A C, Si, GaAs, InP, and/or InGaAs nanotube is formed on the insulating layer and gate dielectric. The nanotube has a central region on the insulating layer above the gate electrode and first and second ends on the gate dielectric. A source is formed on the first end and spaced from the central region and gate electrode by a first peripheral region. A drain is formed on the second end and spaced from the central region and gate electrode by a second peripheral region. The first and second peripheral regions are doped with Cl2, Br2, K, Na, or a molecule of polyethylenimine using wet deposition or evaporation.
摘要翻译：该方法包括在Si背栅上形成1-10000nm厚的SiO 2，HfO 2，Al 2 O 3和/或石英栅极电介质。在栅极电介质上形成Al或Mo栅电极。在栅电极上形成Al 2 O 3绝缘层。在绝缘层和栅极电介质上形成C，Si，GaAs，InP和/或InGaAs纳米管。纳米管在栅电极上方的绝缘层上的中心区域和栅电介质上的第一和第二端。源极在第一端部上形成并且通过第一周边区域与中心区域和栅电极间隔开。在第二端形成漏极，并且通过第二周边区域与中心区域和栅电极间隔开。第一和第二周边区域使用湿沉积或蒸发掺杂有Cl 2，Br 2，K，Na或分子的聚乙烯亚胺。

10. 发明授权

US09190135B2 Organic ferroelectric material based random access memory 有权
标题翻译：基于有机铁电材料的随机存取存储器
公开(公告)号：US09190135B2
公开(公告)日：2015-11-17
申请号：US13566830
申请日：2012-08-03
申请人： Joerg Appenzeller , Saptarshi Das
发明人： Joerg Appenzeller , Saptarshi Das
IPC分类号： G11C11/22 , B82Y10/00 , H01L21/28 , H01L29/51 , H01L29/66 , H01L27/115 , H01L29/06 , H01L29/78
CPC分类号： G11C11/22 , B82Y10/00 , H01L21/28291 , H01L27/1159 , H01L29/0669 , H01L29/516 , H01L29/6684 , H01L29/78391
摘要： Illustrative embodiments provide a FETRAM that is significantly improved over the operation of conventional FeRAM technology. In accordance with at least one disclosed embodiment, a CMOS-processing compatible memory cell provides an architecture enabling a non-destructive read out operation using organic ferroelectric PVDF-TrFE as the memory storage unit and silicon nanowire as the memory read out unit.
摘要翻译：示例性实施例提供了相对于常规FeRAM技术的操作而显着改进的FETRAM。根据至少一个公开的实施例，CMOS处理兼容的存储单元提供使得能够使用有机铁电PVDF-TrFE作为存储器存储单元和硅纳米线作为存储器读出单元进行非破坏性读出操作的架构。

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