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1. 发明申请

US20100244894A1 ENHANCED FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：增强现场可编程门阵列
公开(公告)号：US20100244894A1
公开(公告)日：2010-09-30
申请号：US12794279
申请日：2010-06-04
申请人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

2. 发明授权

US08258811B2 Enhanced field programmable gate array 有权
标题翻译：增强型现场可编程门阵列
公开(公告)号：US08258811B2
公开(公告)日：2012-09-04
申请号：US13158019
申请日：2011-06-10
申请人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

3. 发明授权

US07977970B2 Enhanced field programmable gate array 有权
标题翻译：增强型现场可编程门阵列
公开(公告)号：US07977970B2
公开(公告)日：2011-07-12
申请号：US12794279
申请日：2010-06-04
申请人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

4. 发明授权

US5625301A Flexible FPGA input/output architecture 失效
标题翻译：灵活的FPGA输入/输出架构
公开(公告)号：US5625301A
公开(公告)日：1997-04-29
申请号：US444243
申请日：1995-05-18
申请人： William C. Plants , Sinan Kaptanoglu , Jung-Cheun Lien , King W. Chan , Khaled A. El-Ayat
发明人： William C. Plants , Sinan Kaptanoglu , Jung-Cheun Lien , King W. Chan , Khaled A. El-Ayat
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17704
摘要： An input/output architecture for a field-programmable gate array integrated circuit including a plurality of logic function modules in an array of rows and columns, each of the modules having at least one input conductor and at least one output conductor; a plurality of interconnect conductors, comprising a plurality of input/output pads; a plurality of input/output kernels, each input/output kernel comprising an input buffer having a data input connected to one of the I/O pads and a data output connected to an input buffer data conductor, an output buffer having a data input connected to an output buffer data conductor, a data output connected to the I/O pad, and an enable input connected to an output buffer enable conductor; the input buffer data conductors extending in either the row or the column direction, different ones of the input buffer data conductors extending different numbers of rows or columns, the input buffer data conductors forming first intersections with inputs of the modules; the output buffer data conductors and output buffer enable conductors extending in either the row or the column direction, different ones of the output buffer data conductors and output buffer enable conductors extending different numbers of rows or columns, the input buffer data conductors forming second intersections with outputs of the modules; and user-programmable interconnect elements connected across selected ones of the first and second intersections.
摘要翻译：一种用于现场可编程门阵列集成电路的输入/输出架构，包括行和列阵列中的多个逻辑功能模块，每个模块具有至少一个输入导体和至少一个输出导体; 多个互连导体，包括多个输入/输出焊盘; 多个输入/输出内核，每个输入/输出内核包括输入缓冲器，该输入缓冲器具有连接到I / O焊盘之一的数据输入和连接到输入缓冲器数据导体的数据输出;输出缓冲器，其具有连接的数据输入连接到输出缓冲器数据导体，连接到I / O焊盘的数据输出和连接到输出缓冲器使能导体的使能输入; 输入缓冲器数据导体在行或列方向上延伸，不同的输入缓冲器数据导体延伸不同数量的行或列，输入缓冲器数据导体与模块的输入形成第一交点; 输出缓冲器数据导体和输出缓冲器使能导体在行或列方向上延伸，不同的输出缓冲器数据导体和输出缓冲器使能导体延伸不同数量的行或列，输入缓冲器数据导体与第模块输出; 以及连接在第一和第二交叉点中的选定的互连元件之间的用户可编程互连元件。

5. 发明授权

US5451887A Programmable logic module and architecture for field programmable gate array device 失效
公开(公告)号：US5451887A
公开(公告)日：1995-09-19
申请号：US246218
申请日：1994-05-19
申请人： Khaled A. El-Avat , Sinan Kaptanoglu , King W. Chan , William C. Plants , Jung-Cheun Lien
发明人： Khaled A. El-Avat , Sinan Kaptanoglu , King W. Chan , William C. Plants , Jung-Cheun Lien
IPC分类号： H01L21/82 , G01R31/28 , G01R31/3185 , H03K19/00 , H03K19/173 , H03K19/177
CPC分类号： G01R31/2884 , G01R31/318516 , G01R31/318519 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

6. 发明授权

US5698992A Programmable logic module and architecture for field programmable gate array device 失效
标题翻译：现场可编程门阵列器件的可编程逻辑模块和架构
公开(公告)号：US5698992A
公开(公告)日：1997-12-16
申请号：US746554
申请日：1996-11-13
申请人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
发明人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
IPC分类号： H03K19/177 , G01R31/28 , G01R31/3185 , H03K19/173
CPC分类号： G01R31/2884 , G01R31/318519 , H03K19/17704 , H03K19/17728
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.
摘要翻译：用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。包括本地互连通道的本地互连架构也被施加在阵列上。每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

7. 发明授权

US5570041A Programmable logic module and architecture for field programmable gate array device 失效
公开(公告)号：US5570041A
公开(公告)日：1996-10-29
申请号：US504051
申请日：1995-06-28
申请人： Khaled A. El-Avat , Sinan Kaptanoglu , King W. Chan , William C. Plants , Jung-Cheun Lien
发明人： Khaled A. El-Avat , Sinan Kaptanoglu , King W. Chan , William C. Plants , Jung-Cheun Lien
IPC分类号： H01L21/82 , G01R31/28 , G01R31/3185 , H03K19/00 , H03K19/173 , H03K19/177
CPC分类号： G01R31/2884 , G01R31/318516 , G01R31/318519 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

8. 发明授权

US5477165A Programmable logic module and architecture for field programmable gate array device 失效
标题翻译：现场可编程门阵列器件的可编程逻辑模块和架构
公开(公告)号：US5477165A
公开(公告)日：1995-12-19
申请号：US332550
申请日：1994-12-28
申请人： Khaled A. ElAyat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
发明人： Khaled A. ElAyat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
IPC分类号： H03K19/177 , G01R31/28 , G01R31/3185 , H03K19/173
CPC分类号： G01R31/2884 , G01R31/318519 , H03K19/17704 , H03K19/17728
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.
摘要翻译：用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。包括本地互连通道的本地互连架构也被施加在阵列上。每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

9. 发明授权

US5606267A Programmable logic module and architecture for field programmable gate array device 失效
公开(公告)号：US5606267A
公开(公告)日：1997-02-25
申请号：US522945
申请日：1995-09-01
申请人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
发明人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
IPC分类号： H03K19/177 , G01R31/28 , G01R31/3185 , H03K19/173
CPC分类号： G01R31/2884 , G01R31/318519 , H03K19/17704 , H03K19/17728
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

10. 发明授权

US5744980A Flexible, high-performance static RAM architecture for field-programmable gate arrays 失效
标题翻译：用于现场可编程门阵列的灵活高性能静态RAM架构
公开(公告)号：US5744980A
公开(公告)日：1998-04-28
申请号：US603597
申请日：1996-02-16
申请人： John E. McGowan , William C. Plants , Joel D. Landry , Sinan Kaptanoglu , Warren K. Miller
发明人： John E. McGowan , William C. Plants , Joel D. Landry , Sinan Kaptanoglu , Warren K. Miller
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17704
摘要： A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors are segmented by user-programmable interconnect elements, and some horizontal and vertical interconnect conductors are connectable by user-programmable interconnect elements located at selected intersections between them. An array of rows and columns of logic function modules each having at least one input and one output is superimposed on the routing channels. The inputs and outputs of the logic function modules are connectable to ones of the interconnect conductors in either or both of the horizontal and vertical routing channels. At least one column of random access memory blocks is disposed in the array. Each random access memory block spans a distance of more than one row of the array such that more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof. Each of the random access memory blocks has address inputs, control inputs, data inputs, and data outputs. User-programmable interconnect elements are connected between the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks and selected ones of the interconnect conductors in the horizontal routing channels passing therethrough. Programming circuitry is provided for programming selected ones of the user-programmable interconnect conductors to connect the inputs and outputs of the logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks.
摘要翻译：现场可编程门阵列架构包括多个水平和垂直路由通道，每个路由通道包括多个互连导体。一些互连导体由用户可编程互连元件分段，并且一些水平和垂直互连导体可由位于它们之间的选定交叉处的用户可编程互连元件连接。每个具有至少一个输入和一个输出的逻辑功能模块的行和列阵列叠加在路由信道上。逻辑功能模块的输入和输出可连接到水平和垂直路由通道中的一个或两者中的互连导体中的一个。至少一列随机存取存储器块被布置在阵列中。每个随机存取存储器块跨越阵列的多于一行的距离，使得多于一个的水平路由信道通过其中并且可连接到其任一侧的相邻逻辑功能模块。每个随机存取存储块具有地址输入，控制输入，数据输入和数据输出。用户可编程互连元件连接在随机存取存储器块的地址输入，控制输入，数据输入和数据输出以及通过其中的水平路由通道中的选定的互连导体。提供了编程电路，用于编程用户可编程互连导体中的所选择的一个以将逻辑功能模块的输入和输出彼此连接，并将随机存取存储器块的地址输入，控制输入，数据输入和数据输出。

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