专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08316327B2 Methods of optical proximity correction 有权
标题翻译：光学邻近校正方法
公开(公告)号：US08316327B2
公开(公告)日：2012-11-20
申请号：US13089955
申请日：2011-04-19
申请人： Klaus Herold
发明人： Klaus Herold
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Systems and methods of optical proximity correction are disclosed. A preferred embodiment comprises a method of determining optical proximity correction, which includes providing a design for a lithography mask. The design comprises a layout for a material layer of a semiconductor device. A predicted wafer image producible by the design for the lithography mask is calculated, and an amount of error between a target image and the calculated predicted wafer image is measured over a plurality of pixels of the predicted wafer image. The plurality of pixels comprises a plurality of different sizes.
摘要翻译：公开了光学邻近校正的系统和方法。优选实施例包括确定光学邻近校正的方法，其包括提供光刻掩模的设计。该设计包括用于半导体器件的材料层的布局。计算通过光刻掩模的设计产生的预测晶片图像，并且在预测晶片图像的多个像素上测量目标图像与计算出的预测晶片图像之间的误差量。多个像素包括多个不同的尺寸。

2. 发明授权

US08039203B2 Integrated circuits and methods of design and manufacture thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US08039203B2
公开(公告)日：2011-10-18
申请号：US12126741
申请日：2008-05-23
申请人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
发明人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70 , H01L21/0274 , H01L21/28123 , H01L21/823437 , Y10S438/942
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括在半导体衬底上沉积栅极材料，并且在栅极材料上沉积第一抗蚀剂层。使用第一掩模来图案化第一抗蚀剂层以形成第一和第二抗蚀剂特征。第一抗蚀剂特征包括半导体器件的栅极线的图案，第二抗蚀剂特征包括印刷辅助特征。使用第二掩模形成抗蚀剂模板; 第二掩模移除第二抗蚀剂特征。

3. 发明申请

US20100175041A1 ADJUSTMENT OF MASK SHAPES FOR IMPROVING PRINTABILITY OF DENSE INTEGRATED CIRCUIT LAYOUT 有权
标题翻译：调整密封形状的改进打印电路集成电路布局的可打印性
公开(公告)号：US20100175041A1
公开(公告)日：2010-07-08
申请号：US12348331
申请日：2009-01-05
申请人： Azalia Krasnoperova , Ian P. Stobert , Klaus Herold
发明人： Azalia Krasnoperova , Ian P. Stobert , Klaus Herold
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided.
摘要翻译：本发明的实施例提供一种用于制作掩模形状调整的方法。该方法包括产生第一掩模形状; 识别第一掩模形状的一个或多个掩模段作为需要段调整的候选掩码段; 将光学邻近校正（OPC）处理应用于所述第一掩模形状，所述OPC处理将所述候选掩模段中的至少一个识别为约束掩模段; 对受约束的掩模段施加旋转调节; 以及创建具有被约束的掩模段被旋转地调节的第二掩模形状。还提供了用于执行上述方法的系统和机器可读介质。

4. 发明授权

US07553703B2 Methods of forming an interconnect structure 有权
标题翻译：形成互连结构的方法
公开(公告)号：US07553703B2
公开(公告)日：2009-06-30
申请号：US12014539
申请日：2008-01-15
申请人： Klaus Herold , Erdem Kaltalioglu
发明人： Klaus Herold , Erdem Kaltalioglu
IPC分类号： H01L21/82 , H01L23/48
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a second conductive feature of the interconnect structure is extended by a second distance, the second distance being different than the first distance. Ends of conductive features that are positioned close to adjacent conductive features are preferably not extended.
摘要翻译：公开了具有延伸端的导电线的半导体器件和将导线端部延伸可变距离的方法。互连结构的第一导电特征的端部延伸第一距离，并且互连结构的第二导电特征的端部延伸第二距离，第二距离不同于第一距离。位于靠近相邻导电特征的导电特征端部优选地不延伸。

5. 发明授权

US07332812B2 Memory card with connecting portions for connection to an adapter 有权
标题翻译：存储卡，带有用于连接到适配器的连接部分
公开(公告)号：US07332812B2
公开(公告)日：2008-02-19
申请号：US11105879
申请日：2005-04-14
申请人： Klaus Herold , Erdem Kaltalioglu
发明人： Klaus Herold , Erdem Kaltalioglu
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a second conductive feature of the interconnect structure is extended by a second distance, the second distance being different than the first distance. Ends of conductive features that are positioned close to adjacent conductive features are preferably not extended.
摘要翻译：公开了具有延伸端的导电线的半导体器件和将导线端部延伸可变距离的方法。互连结构的第一导电特征的端部延伸第一距离，并且互连结构的第二导电特征的端部延伸第二距离，第二距离不同于第一距离。位于靠近相邻导电特征的导电特征端部优选地不延伸。

6. 发明授权

US07666800B2 Feature patterning methods 有权
标题翻译：特征图案化方法
公开(公告)号：US07666800B2
公开(公告)日：2010-02-23
申请号：US12030810
申请日：2008-02-13
申请人： Sajan Marokkey , Alois Gutmann , Klaus Herold , Chandrasekhar Sarma
发明人： Sajan Marokkey , Alois Gutmann , Klaus Herold , Chandrasekhar Sarma
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： Methods of patterning features of semiconductor devices and methods of processing and fabricating semiconductor devices are disclosed. In one embodiment, a method of processing a semiconductor device includes forming first sidewall spacers on a first hard mask, removing the first hard mask, and forming a first material layer over the first sidewall spacers. A second hard mask is formed over the first material layer and the first sidewall spacers. Second sidewall spacers are formed on the second hard mask, and the second hard mask is removed. At least the first sidewall spacers are patterned using the second sidewall spacers as a mask.
摘要翻译：公开了半导体器件的图案化特征的方法和半导体器件的处理和制造方法。在一个实施例中，一种处理半导体器件的方法包括在第一硬掩模上形成第一侧壁间隔物，去除第一硬掩模，以及在第一侧壁间隔物上形成第一材料层。在第一材料层和第一侧壁间隔物上形成第二硬掩模。在第二硬掩模上形成第二侧壁间隔物，并且去除第二硬掩模。至少使用第二侧壁间隔件作为掩模来图案化第一侧壁间隔物。

7. 发明申请

US20090081563A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20090081563A1
公开(公告)日：2009-03-26
申请号：US12126741
申请日：2008-05-23
申请人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
发明人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
IPC分类号： G03F1/14 , G03F7/26
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70 , H01L21/0274 , H01L21/28123 , H01L21/823437 , Y10S438/942
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括在半导体衬底上沉积栅极材料，并且在栅极材料上沉积第一抗蚀剂层。使用第一掩模来图案化第一抗蚀剂层以形成第一和第二抗蚀剂特征。第一抗蚀剂特征包括半导体器件的栅极线的图案，第二抗蚀剂特征包括印刷辅助特征。使用第二掩模形成抗蚀剂模板; 第二掩模移除第二抗蚀剂特征。

8. 发明授权

US08518820B2 Methods for forming contacts in semiconductor devices 有权
标题翻译：在半导体器件中形成触点的方法
公开(公告)号：US08518820B2
公开(公告)日：2013-08-27
申请号：US13301196
申请日：2011-11-21
申请人： Roberto Schiwon , Klaus Herold , Jenny Lian , Sajan Marokkey , Martin Ostermayr
发明人： Roberto Schiwon , Klaus Herold , Jenny Lian , Sajan Marokkey , Martin Ostermayr
IPC分类号： H01L21/4763
CPC分类号： H01L27/105 , G03F1/00 , G03F7/0035 , H01L21/0274 , H01L21/31144 , H01L21/76816 , H01L27/0207 , H01L27/1116
摘要： Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.
摘要翻译：描述了用于在设备中形成触点的掩模套，布局设计和方法。在一个实施例中，半导体器件包括设置在衬底上的多个触点，多个触点被布置为正交格栅上的行和列，多个触点的每一行与多个触点的相邻行间隔开并且所述多个触点中的每一列与所述多个触点的相邻列间隔开第二距离。

9. 发明授权

US08015511B2 Adjustment of mask shapes for improving printability of dense integrated circuit layout 有权
标题翻译：调整面罩形状，提高密集集成电路布局的可印刷性
公开(公告)号：US08015511B2
公开(公告)日：2011-09-06
申请号：US12348331
申请日：2009-01-05
申请人： Azalia Krasnoperova , Ian P Stobert , Klaus Herold
发明人： Azalia Krasnoperova , Ian P Stobert , Klaus Herold
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided.
摘要翻译：本发明的实施例提供一种用于制作掩模形状调整的方法。该方法包括产生第一掩模形状; 识别第一掩模形状的一个或多个掩模段作为需要段调整的候选掩码段; 将光学邻近校正（OPC）处理应用于所述第一掩模形状，所述OPC处理将所述候选掩模段中的至少一个识别为约束掩模段; 对受约束的掩模段施加旋转调节; 以及创建具有被约束的掩模段被旋转地调节的第二掩模形状。还提供了用于执行上述方法的系统和机器可读介质。

10. 发明申请

US20100187611A1 Contacts in Semiconductor Devices 审中-公开
标题翻译：半导体器件联系人
公开(公告)号：US20100187611A1
公开(公告)日：2010-07-29
申请号：US12360599
申请日：2009-01-27
申请人： Roberto Schiwon , Klaus Herold , Jenny Lian , Sajan Marokkey , Martin Ostermayr
发明人： Roberto Schiwon , Klaus Herold , Jenny Lian , Sajan Marokkey , Martin Ostermayr
IPC分类号： H01L27/11 , H01L21/04 , H01L23/48
CPC分类号： H01L27/105 , G03F1/00 , G03F7/0035 , H01L21/0274 , H01L21/31144 , H01L21/76816 , H01L27/0207 , H01L27/1116
摘要： Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.
摘要翻译：描述了用于在设备中形成触点的掩模套，布局设计和方法。在一个实施例中，半导体器件包括设置在衬底上的多个触点，多个触点被布置为正交格栅上的行和列，多个触点的每一行与多个触点的相邻行间隔开并且所述多个触点中的每一列与所述多个触点的相邻列间隔开第二距离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式