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1. 发明授权

US07345530B1 Regulated switch driving scheme in switched-capacitor amplifiers with opamp-sharing 有权
标题翻译：具有运算放大器共享的开关电容放大器的调节开关驱动方案
公开(公告)号：US07345530B1
公开(公告)日：2008-03-18
申请号：US11421716
申请日：2006-06-01
申请人： Jipeng Li , Matthew Courcy , Gabriele Manganaro
发明人： Jipeng Li , Matthew Courcy , Gabriele Manganaro
IPC分类号： H03F1/02
CPC分类号： H03F3/005
摘要： A switched-capacitor amplifier circuit including first and second pairs of sampling capacitors for sampling a pair of input signals includes a voltage regulator coupled to receive a first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage; a clock signal generator generating first and second clock signals referenced to the first power supply voltage and third and fourth clock signals referenced to the first regulated output voltage; and a first set of switches coupling the bottom plates of the sampling capacitors to the amplifier, the first set of switches being controlled by the third and fourth clock signals. The circuit may further include a second set of switches coupling the top plates of the sampling capacitors to the input signals, the second set of switches being controlled by the first and second clock signals.
摘要翻译：包括用于对一对输入信号进行采样的第一和第二对采样电容器的开关电容放大器电路包括耦合以接收第一参考电压并产生与第一参考电压有关的第一调节输出电压的电压调节器，并且独立于第一电源电压; 产生参考第一电源电压的第一和第二时钟信号的时钟信号发生器和参考第一调节输出电压的第三和第四时钟信号; 以及将采样电容器的底板耦合到放大器的第一组开关，第一组开关由第三和第四时钟信号控制。电路还可以包括将采样电容器的顶板耦合到输入信号的第二组开关，第二组开关由第一和第二时钟信号控制。

2. 发明授权

US07372386B1 Parallel digital-to-analog-converter 有权
标题翻译：并行数模转换器
公开(公告)号：US07372386B1
公开(公告)日：2008-05-13
申请号：US11556104
申请日：2006-11-02
申请人： Franco Maloberti , Gabriele Manganaro
发明人： Franco Maloberti , Gabriele Manganaro
IPC分类号： H03M1/66
CPC分类号： H03M1/0626 , H03M1/0836 , H03M1/1215 , H03M1/661
摘要： A method for performing parallel digital-to-analog conversion of an n-bit digital input data signal at a frequency of fs including receiving the n-bit digital input data signal; generating M−1 delayed input data signals, M being the number of parallel conversions channels, the M−1 delayed input data signals having respective increasing amount of unit delay, the digital input data signal and the M−1 delayed input data signals forming M digital signals; holding the M digital signals for a first time period; performing a data transformation of the M digital signals using an M×M Hadamard matrix; generating M (n+m)-bit transformed digital data signals; converting each of the M transformed digital data signals to M analog signals; and performing a reverse data transformation of the M analog signals based on the M×M Hadamard matrix to generate an output analog signal indicative of the n-bit digital input data signal.
摘要翻译：一种用于以包括接收n位数字输入数据信号的频率f进行n位数字输入数据信号的并行数模转换的方法，产生M-1个延迟的输入数据信号，M是并行转换通道的数量，M-1个延迟的输入数据信号具有各自增加的单位延迟量，数字输入数据信号和M-1个延迟的输入数据信号形成M 数字信号; 持续M数字信号第一时间段; 使用MxM Hadamard矩阵执行M个数字信号的数据变换; 产生M（n + m）位变换数字数据信号; 将M个经变换的数字数据信号中的每一个转换为M个模拟信号; 以及基于MxM Hadamard矩阵执行M个模拟信号的反向数据变换，以产生表示n位数字输入数据信号的输出模拟信号。

3. 发明授权

US06778121B2 High linearity digital-to-analog converter 有权
公开(公告)号：US06778121B2
公开(公告)日：2004-08-17
申请号：US10462086
申请日：2003-06-13
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： H03M166
CPC分类号： H03M1/804
摘要： A digital-to-analog converter (DAC) with high linearity includes a switched capacitor amplifier removably coupled to a capacitor array. The result of the conversion by the capacitor array is sampled by the switched capacitor amplifier directly from the capacitor in the most significant cell in the array. The switched capacitor amplifier includes a memory capacitor and a feedback capacitor. The memory capacitor provides the initial output voltage corresponding to the result of the conversion when coupled to the capacitor array and stores the output voltage while the feedback capacitor is reset.

4. 发明申请

US20070247342A1 Methods and apparatus to balance reference settling in switched-capacitor pipelined digital to analog converter 有权
标题翻译：开关电容流水线数模转换器平衡参考稳定的方法和装置
公开(公告)号：US20070247342A1
公开(公告)日：2007-10-25
申请号：US11811718
申请日：2007-06-12
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： H03M1/66
CPC分类号： H03M1/0881 , H03M1/72
摘要： The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.
摘要翻译：通过平衡其预充电开关的稳定特性，开关电容器，管线数模转换器的线性度得到改善。更详细地，开关电容器DAC包括多个基本上相同的单元，输入数字字的每个位的一个单元。使用多个开关驱动器电路来施加相应的开关控制信号以打开和关闭相应的开关。有利的是，开关控制信号的差异被确定为均衡不同开关之间的栅极 - 源极电压差。

5. 发明授权

US06542017B2 Feed-forward approach for timing skew in interleaved and double-sampled circuits 有权
公开(公告)号：US06542017B2
公开(公告)日：2003-04-01
申请号：US09880551
申请日：2001-06-13
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： G06F104
CPC分类号： G11C27/026 , H03K5/1515 , H03M1/1215
摘要： The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having approximately the same frequency for use in sampling an analog signal in a generally alternating fashion. The clock generator circuit further comprises a pre-phase clock generator subcircuit associated with the clock generator subcircuit which is operable to generate two pre-phase clock signals, wherein each are associated with a respective one of the two clock signals generated by the clock generator subcircuit. In the pre-phase clock generator circuit, a signal transition of each of the pre-phase clock signals occurs before a signal transition of the respective clock signal generated by the clock generator subcircuit; in addition, a timing of a falling edge of the pre-phase clock signals is dictated by a global clock signal. Thus the clock generator circuit avoids sampling error in a double-sampled sample and hold circuit and harmonic distortion associated therewith.

6. 发明授权

US07161412B1 Analog calibration of a current source array at low supply voltages 有权
标题翻译：在低电源电压下对电流源阵列进行模拟校准
公开(公告)号：US07161412B1
公开(公告)日：2007-01-09
申请号：US11153938
申请日：2005-06-15
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： G05F3/02
CPC分类号： H03M1/1057
摘要： A calibration circuit for a current source cell includes a reference current source and a transresistance amplifier forming a feedback loop for calibrating the output current of the current source cell. The reference current source supplies a reference current to a first node switchably connected to the current output node of the current source cell. The transresistance amplifier has an input terminal coupled to the first node and an output terminal switchably connected to a calibration node of the current source cell. With the calibration circuit coupled for calibration, an input current develops at the first node being the difference between the output current of the current source cell and the reference current. The transresistance amplifier receives the input current and generates an output voltage for driving the calibration node. The output voltage has a value operative to nullify the difference between the output current and the reference current.
摘要翻译：用于电流源单元的校准电路包括参考电流源和跨阻放大器，其形成用于校准电流源单元的输出电流的反馈环路。参考电流源向可切换地连接到当前源单元的当前输出节点的第一节点提供参考电流。跨阻放大器具有耦合到第一节点的输入端子和可切换地连接到当前源单元的校准节点的输出端子。通过校准电路耦合用于校准，在第一节点处产生的输入电流是电流源单元的输出电流与参考电流之间的差。跨阻放大器接收输入电流并产生用于驱动校准节点的输出电压。输出电压有一个值可以消除输出电流和参考电流之间的差异。

7. 发明申请

US20050073452A1 Methods and apparatus to balance reference settling in switched-capacitor pipelined digital to analog converter 有权
标题翻译：开关电容流水线数模转换器平衡参考稳定的方法和装置
公开(公告)号：US20050073452A1
公开(公告)日：2005-04-07
申请号：US10947646
申请日：2004-09-22
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： H03M1/72 , H03M1/66
CPC分类号： H03M1/0881 , H03M1/72
摘要： The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.
摘要翻译：通过平衡其预充电开关的稳定特性，开关电容器，管线数模转换器的线性度得到改善。更详细地，开关电容器DAC包括多个基本上相同的单元，输入数字字的每个位的一个单元。使用多个开关驱动器电路来施加相应的开关控制信号以打开和关闭相应的开关。有利的是，开关控制信号的差异被确定为均衡不同开关之间的栅极 - 源极电压差。

8. 发明授权

US6061672A Fuzzy logic neural network modular architecture 失效
标题翻译：模糊逻辑神经网络模块化架构
公开(公告)号：US6061672A
公开(公告)日：2000-05-09
申请号：US953158
申请日：1997-10-17
申请人： Riccardo Caponetto , Luigi Occhipinti , Luigi Fortuna , Gabriele Manganaro , Gaetano Giudice
发明人： Riccardo Caponetto , Luigi Occhipinti , Luigi Fortuna , Gabriele Manganaro , Gaetano Giudice
IPC分类号： G06F15/18 , G06F9/44 , G06F15/80 , G06N3/00 , G06N3/04 , G06N7/02 , G06N7/04
CPC分类号： G06N7/046 , G06F15/803
摘要： The invention relates to a modular architecture of a cellular network for improved large-scale integration, of the type which comprises a plurality of fuzzy cellular elements (C.sub.m,n) interconnected to form a matrix of elements having at least m rows and n columns, the row and column numbers describing the location of each element. Each fuzzy processor is adapted for connection to other processors of the same type such that a parallel architecture of the modular type can be implemented. The management of the architecture is facilitated by each submatrix being controlled by an individually dedicated fuzzy processor device.
摘要翻译：本发明涉及用于改进大规模集成的蜂窝网络的模块化架构，其类型包括多个互连以形成具有至少m行和n列的元素矩阵的模糊蜂窝元件（Cm，n）描述每个元素的位置的行和列号。每个模糊处理器适于连接到相同类型的其他处理器，使得可以实现模块化类型的并行架构。每个子矩阵由单独专用的模糊处理器设备控制，便于对架构的管理。

9. 发明授权

US07403148B2 Methods and apparatus to balance reference settling in switched-capacitor pipelined digital to analog converter 有权
标题翻译：开关电容流水线数模转换器平衡参考稳定的方法和装置
公开(公告)号：US07403148B2
公开(公告)日：2008-07-22
申请号：US11811718
申请日：2007-06-12
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： H03M1/66
CPC分类号： H03M1/0881 , H03M1/72
摘要： The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.
摘要翻译：通过平衡其预充电开关的稳定特性，开关电容器，管线数模转换器的线性度得到改善。更详细地，开关电容器DAC包括多个基本上相同的单元，输入数字字的每个位的一个单元。使用多个开关驱动器电路来施加相应的开关控制信号以打开和关闭相应的开关。有利的是，开关控制信号的差异被确定为均衡不同开关之间的栅极 - 源极电压差。

10. 发明授权

US07324034B2 Methods and apparatus to balance reference settling in switched-capacitor pipelined digital to analog converter 有权
公开(公告)号：US07324034B2
公开(公告)日：2008-01-29
申请号：US10947646
申请日：2004-09-22
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： H03M1/66
CPC分类号： H03M1/0881 , H03M1/72
摘要： The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.

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