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1. 发明授权

US07345530B1 Regulated switch driving scheme in switched-capacitor amplifiers with opamp-sharing 有权
标题翻译：具有运算放大器共享的开关电容放大器的调节开关驱动方案
公开(公告)号：US07345530B1
公开(公告)日：2008-03-18
申请号：US11421716
申请日：2006-06-01
申请人： Jipeng Li , Matthew Courcy , Gabriele Manganaro
发明人： Jipeng Li , Matthew Courcy , Gabriele Manganaro
IPC分类号： H03F1/02
CPC分类号： H03F3/005
摘要： A switched-capacitor amplifier circuit including first and second pairs of sampling capacitors for sampling a pair of input signals includes a voltage regulator coupled to receive a first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage; a clock signal generator generating first and second clock signals referenced to the first power supply voltage and third and fourth clock signals referenced to the first regulated output voltage; and a first set of switches coupling the bottom plates of the sampling capacitors to the amplifier, the first set of switches being controlled by the third and fourth clock signals. The circuit may further include a second set of switches coupling the top plates of the sampling capacitors to the input signals, the second set of switches being controlled by the first and second clock signals.
摘要翻译：包括用于对一对输入信号进行采样的第一和第二对采样电容器的开关电容放大器电路包括耦合以接收第一参考电压并产生与第一参考电压有关的第一调节输出电压的电压调节器，并且独立于第一电源电压; 产生参考第一电源电压的第一和第二时钟信号的时钟信号发生器和参考第一调节输出电压的第三和第四时钟信号; 以及将采样电容器的底板耦合到放大器的第一组开关，第一组开关由第三和第四时钟信号控制。电路还可以包括将采样电容器的顶板耦合到输入信号的第二组开关，第二组开关由第一和第二时钟信号控制。

2. 发明授权

US07372391B1 Pipeline ADC with memory effects achieving one cycle absolute over-range recovery 有权
标题翻译：具有记忆效应的管道ADC实现一个周期绝对超范围恢复
公开(公告)号：US07372391B1
公开(公告)日：2008-05-13
申请号：US11677358
申请日：2007-02-21
申请人： Matthew Courcy , Jipeng Li
发明人： Matthew Courcy , Jipeng Li
IPC分类号： H03M1/38
CPC分类号： H03M1/129 , H03M1/0607 , H03M1/0695 , H03M1/1215 , H03M1/44
摘要： A data conversion stage circuit (104) for an opamp-shared pipeline analog-to-digital converter (ADC) (100) includes an over-range detection and recovery circuit including first and second switches (S3, S4) connected between respective input terminals (136, 137) and output terminals (138, 139) of the opamp (128) and both controlled by a first control signal, and a logic circuit (150) coupled to receive the first residue value and compare the first residue value to a pair of high and low comparison voltage levels. The logic circuit asserts the first control signal during a first clock phase when the first residue value is either greater than the high comparison voltage level or less than the low comparison voltage level. The high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit where the reference voltage range defines in-range voltage values for the data conversion stage circuit.
摘要翻译：一种用于运算放大器共享流水线模数转换器（ADC）（100）的数据转换级电路（104）包括超范围检测和恢复电路，包括连接在各自之间的第一和第二开关（S 3，S 4）输入端子（136,137）和运算放大器（128）的输出端子（138,139），并且均由第一控制信号控制;以及逻辑电路（150），耦合以接收第一残余值并比较第一残留值达到一对高低比较电压电平。当第一个残余值大于高比较电压电平或小于低比较电压电平时，逻辑电路在第一时钟相位期间断言第一控制信号。高和低比较电压电平定义了数据转换级电路的参考电压范围之外的电压区域，其中参考电压范围限定数据转换级电路的范围内的电压值。

3. 发明授权

US09219410B2 Charge pump supply with clock phase interpolation 有权
标题翻译：电荷泵电源带时钟相位插补
公开(公告)号：US09219410B2
公开(公告)日：2015-12-22
申请号：US13617548
申请日：2012-09-14
申请人： Jipeng Li , Richard E. Schreier
发明人： Jipeng Li , Richard E. Schreier
IPC分类号： G05F1/10 , G05F3/02 , H02M3/07
CPC分类号： H02M3/073 , H02M2003/077
摘要： A voltage generator may include a plurality of charge pumps, plural sets of delay pipelines and a phase controller. Given M delay pipelines having N stages each, there may be M*N charge pumps each having a triggering input coupled to a respective stage or a respective pipeline. The phase controller may include a plurality of phase control stages interconnecting among the delay pipelines to induce timing offsets among the outputs of the delay stage. In an alternate design, intermediate nodes among the pipeline's delay stages may be coupled to triggering inputs of a sub-set of the charge pumps. The phase controller may have a plurality of phase control stages coupled, respectively, between the intermediate nodes of the delay pipeline and intermediate nodes of the phase control stages may be coupled to triggering inputs of another sub-set of the charge pumps.
摘要翻译：电压发生器可以包括多个电荷泵，多组延迟管线和相位控制器。给定每个具有N个级的M个延迟管线，可以有M * N个电荷泵，每个具有耦合到相应级或相应流水线的触发输入。相位控制器可以包括在延迟管线之间互连的多个相位控制级，以在延迟级的输出之间引起定时偏移。在替代设计中，管线延迟级之间的中间节点可以耦合到电荷泵的子集的触发输入。相位控制器可以具有分别在延迟流水线的中间节点之间耦合的多个相位控制级，并且相位控制级的中间节点可耦合到电荷泵的另一子集的触发输入。

4. 发明授权

US08860491B1 Integrator output swing reduction technique for sigma-delta analog-to-digital converters 有权
标题翻译：用于Σ-Δ模数转换器的积分器输出摆幅减小技术
公开(公告)号：US08860491B1
公开(公告)日：2014-10-14
申请号：US13937627
申请日：2013-07-09
申请人： Jipeng Li
发明人： Jipeng Li
IPC分类号： G06F7/64
CPC分类号： H03M3/442
摘要： Embodiments of the present invention may include an apparatus and method to reduce an output swing in each stage of a multi-stage loop filter while also maintaining a desired signal transfer function for each respective stage. A given stage of the loop filter may include an integrator, a feedback path, a first cancellation path, and a second cancellation path. The first cancellation path may be coupled to the output of the integrator. The second cancellation path may be coupled to a feedback path provided about the input and output of the integrator. A first cancellation signal may be injected into the first cancellation path to reduce the output swing of the integrator. A second cancellation signal may be injected into the second cancellation path to minimize a change in the integrator's signal transfer function caused by the first cancellation signal.
摘要翻译：本发明的实施例可以包括减少多级环路滤波器的每个级中的输出摆幅的装置和方法，同时还保持每个相应级的期望的信号传递函数。环路滤波器的给定级可以包括积分器，反馈路径，第一消除路径和第二消除路径。第一消除路径可以耦合到积分器的输出端。第二消除路径可以耦合到围绕积分器的输入和输出提供的反馈路径。可以将第一抵消信号注入到第一消除路径中以减小积分器的输出摆幅。可以将第二抵消信号注入到第二消除路径中以最小化由第一消除信号引起的积分器的信号传递函数的变化。

5. 发明授权

US08031098B1 DAC circuit with pseudo-return-to-zero scheme and DAC calibration circuit and method 有权
标题翻译： DAC电路采用伪归零方案和DAC校准电路及方法
公开(公告)号：US08031098B1
公开(公告)日：2011-10-04
申请号：US12689874
申请日：2010-01-19
申请人： Christian Ebner , Jipeng Li , Bernd Schafferer
发明人： Christian Ebner , Jipeng Li , Bernd Schafferer
IPC分类号： H03M1/72
CPC分类号： H03M1/1061 , H03M1/747 , H03M3/464
摘要： In one embodiment, digital-to-analog converter (DAC) circuit includes dual DAC units employing pseudo-return-to-zero DAC operations to reduce inter-symbol interference. Moreover, each DAC unit is implemented using complementary MOS transistors to improve conversion performance. In another embodiment, a DAC calibration scheme performs background calibration of an array of DAC circuits in continuous time using a reference DAC circuit and a spare DAC circuit. Calibration (also referred to as “trimming”) of the DAC circuit using the calibration scheme of the present invention ensures that the DAC operates with high linearity over process variations. In one embodiment, the DAC circuit and the DAC calibration scheme are applied as the feedback DAC in a continuous-time sigma-delta (CT-ΣΔ) analog-to-digital converter to realize high performance and high precision analog-to-digital conversions.
摘要翻译：在一个实施例中，数模转换器（DAC）电路包括采用伪返归至零DAC操作的双DAC单元，以减少符号间干扰。此外，每个DAC单元使用互补MOS晶体管实现，以提高转换性能。在另一个实施例中，DAC校准方案使用参考DAC电路和备用DAC电路在连续时间内执行DAC电路阵列的背景校准。使用本发明的校准方案的DAC电路的校准（也称为“修整”）确保了DAC在工艺变化上以高线性度运行。在一个实施例中，DAC电路和DAC校准方案作为反馈DAC应用于连续时间Σ-Δ（CT-＆Sgr＆amp; Dgr）模数转换器，以实现高性能和高精度的模数转换数字转换。

6. 发明申请

US20140078795A1 CHARGE PUMP SUPPLY WITH CLOCK PHASE INTERPOLATION 有权
标题翻译：充电泵供应时钟相位插值
公开(公告)号：US20140078795A1
公开(公告)日：2014-03-20
申请号：US13617548
申请日：2012-09-14
申请人： Jipeng Li , Richard E. Schreier
发明人： Jipeng Li , Richard E. Schreier
IPC分类号： H02M3/18
CPC分类号： H02M3/073 , H02M2003/077
摘要： A voltage generator may include a plurality of charge pumps, plural sets of delay pipelines and a phase controller. Given M delay pipelines having N stages each, there may be M*N charge pumps each having a triggering input coupled to a respective stage or a respective pipeline. The phase controller may include a plurality of phase control stages interconnecting among the delay pipelines to induce timing offsets among the outputs of the delay stage. In an alternate design, intermediate nodes among the pipeline's delay stages may be coupled to triggering inputs of a sub-set of the charge pumps. The phase controller may have a plurality of phase control stages coupled, respectively, between the intermediate nodes of the delay pipeline and intermediate nodes of the phase control stages may be coupled to triggering inputs of another sub-set of the charge pumps.
摘要翻译：电压发生器可以包括多个电荷泵，多组延迟管线和相位控制器。给定每个具有N个级的M个延迟管线，可以有M * N个电荷泵，每个具有耦合到相应级或相应流水线的触发输入。相位控制器可以包括在延迟管线之间互连的多个相位控制级，以在延迟级的输出之间引起定时偏移。在替代设计中，管线延迟级之间的中间节点可以耦合到电荷泵的子集的触发输入。相位控制器可以具有分别在延迟流水线的中间节点之间耦合的多个相位控制级，并且相位控制级的中间节点可以耦合到触发电荷泵的另一子集的触发输入。

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