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1. 发明授权

US08026769B2 Frequency-locked clock generator 有权
标题翻译：频率锁定时钟发生器
公开(公告)号：US08026769B2
公开(公告)日：2011-09-27
申请号：US12637330
申请日：2009-12-14
申请人： Tom Kwan , Niug Li
发明人： Tom Kwan , Niug Li
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H03L7/02
摘要： A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.
摘要翻译：锁频时钟发生器包括压控振荡器（VCO），频率 - 电流转换器，参考电流源和增益级。 VCO产生一个输出信号。频率到电流转换器产生与输出信号的频率成比例的转换器电流。参考电流源产生参考电流。增益级基于转换器电流和参考电流之间的差产生控制信号。控制信号被施加到VCO以调整输出信号的频率。反馈迫使VCO产生输出时钟信号，使得其产生的相应电流（即，转换器电流）等于参考电流。当锁定时，输出信号的频率由锁频时钟发生器的时间常数（或等效时间常数）决定。

2. 发明授权

US07852058B2 Power supply regulator with digital control 有权
公开(公告)号：US07852058B2
公开(公告)日：2010-12-14
申请号：US12685433
申请日：2010-01-11
申请人： Tom Kwan
发明人： Tom Kwan
IPC分类号： G05F1/00
CPC分类号： H02M3/157
摘要： An integrated circuit and method in an integrated circuit for providing electrical power utilizing digital power regulation. Various aspects of the present invention provide an integrated circuit comprising a power supply module that outputs electrical power at an output voltage level. An error determination module may receive a power supply reference signal and a signal indicative of the output voltage level and output a power supply error signal. A digital controller module may receive the power supply error signal, digitally process the power supply error signal, and output a power supply control signal. A power output-monitoring module may monitor the electrical power output from the power supply module and output the signal indicative of the output voltage level. The power supply module may receive the power supply control signal and output the electrical power based, at least in part, on the power supply control signal.

3. 发明申请

US20100134191A1 Frequency-Locked Clock Generator 有权
标题翻译：频率锁定时钟发生器
公开(公告)号：US20100134191A1
公开(公告)日：2010-06-03
申请号：US12637330
申请日：2009-12-14
申请人： Tom KWAN , Niug Li
发明人： Tom KWAN , Niug Li
IPC分类号： H03L7/00 , G06F1/04
CPC分类号： H03L7/00 , H03L7/02
摘要： A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.
摘要翻译：锁频时钟发生器包括压控振荡器（VCO），频率 - 电流转换器，参考电流源和增益级。 VCO产生一个输出信号。频率到电流转换器产生与输出信号的频率成比例的转换器电流。参考电流源产生参考电流。增益级基于转换器电流和参考电流之间的差产生控制信号。控制信号被施加到VCO以调整输出信号的频率。反馈迫使VCO产生输出时钟信号，使得其产生的相应电流（即，转换器电流）等于参考电流。当锁定时，输出信号的频率由锁频时钟发生器的时间常数（或等效时间常数）决定。

4. 发明申请

US20100109632A1 POWER SUPPLY REGULATOR WITH DIGITAL CONTROL 有权
标题翻译：带数字控制的电源调节器
公开(公告)号：US20100109632A1
公开(公告)日：2010-05-06
申请号：US12685433
申请日：2010-01-11
申请人： Tom Kwan
发明人： Tom Kwan
IPC分类号： G05F1/10
CPC分类号： H02M3/157
摘要： An integrated circuit and method in an integrated circuit for providing electrical power utilizing digital power regulation. Various aspects of the present invention provide an integrated circuit comprising a power supply module that outputs electrical power at an output voltage level. An error determination module may receive a power supply reference signal and a signal indicative of the output voltage level and output a power supply error signal. A digital controller module may receive the power supply error signal, digitally process the power supply error signal, and output a power supply control signal. A power output-monitoring module may monitor the electrical power output from the power supply module and output the signal indicative of the output voltage level. The power supply module may receive the power supply control signal and output the electrical power based, at least in part, on the power supply control signal.
摘要翻译：一种用于利用数字功率调节提供电力的集成电路中的集成电路和方法。本发明的各个方面提供一种集成电路，其包括在输出电压电平下输出电力的电源模块。错误确定模块可以接收电源参考信号和指示输出电压电平的信号，并输出电源错误信号。数字控制器模块可以接收电源错误信号，数字处理电源错误信号，并输出电源控制信号。电力输出监视模块可以监视从电源模块输出的电力并输出指示输出电压电平的信号。电源模块可以至少部分地基于电源控制信号来接收电源控制信号并输出电力。

5. 发明申请

US20090268646A1 Line Driver For An Adaptive Hybrid Circuit 有权
标题翻译：自适应混合电路的线路驱动器
公开(公告)号：US20090268646A1
公开(公告)日：2009-10-29
申请号：US12497337
申请日：2009-07-02
申请人： Tom Kwan , Sumant Ranganathan
发明人： Tom Kwan , Sumant Ranganathan
IPC分类号： H04B3/23
CPC分类号： H04L5/1423 , H04L25/0278
摘要： A second output transmission signal (“TX2”) added to a line driver is a scaled version of the main output transmission signal (“TX1”). TX2 is scaled from TX1 by a variable scale factor K. An adaptive hybrid circuit subtracts TX1 and TX2 from a line signal carrying both a line transmission signal and a line received signal (“RX”). A programmable impedance Ztune is coupled between the TX2 output of the line driver and the RX output of the adaptive hybrid circuit. A transmission echo in the output RX signal is measured. K and Ztune are then adaptively tuned to minimize the transmission echo. The hybrid in this case becomes a 4-port network, one port specifically added to adaptively cancel the transmission echo in the RX output of the adaptive hybrid circuit. Alternatively, the hybrid may be a 3-port hybrid including variable impedances to cancel the line transmission signal.
摘要翻译：添加到线路驱动器的第二输出发送信号（“TX2”）是主输出发送信号（“TX1”）的缩放版本。 TX2通过可变比例因子K从TX1缩放。自适应混合电路从携带线路传输信号和线路接收信号（“RX”）的线路信号中减去TX1和TX2。可编程阻抗Ztune耦合在线路驱动器的TX2输出和自适应混合电路的RX输出之间。测量输出RX信号中的传输回波。然后自适应调整K和Ztune以最小化传输回波。在这种情况下，混合器成为一个4端口网络，一个专门添加的端口自适应地消除了自适应混合电路的RX输出中的传输回波。或者，混合动力可以是包括可变阻抗以消除线路传输信号的3端口混合器。

6. 发明申请

US20060192614A1 Gigabit ethernet transceiver with analog front end 有权
公开(公告)号：US20060192614A1
公开(公告)日：2006-08-31
申请号：US11345946
申请日：2006-02-02
申请人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03B1/00
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

7. 发明申请

US20050238123A1 Method and system for charge sensing with variable gain, offset compensation, and demodulation 有权
标题翻译：具有可变增益，偏移补偿和解调的电荷感测方法和系统
公开(公告)号：US20050238123A1
公开(公告)日：2005-10-27
申请号：US11115226
申请日：2005-04-27
申请人： Sumant Ranganathan , Tom Kwan , Hung-Sung Li
发明人： Sumant Ranganathan , Tom Kwan , Hung-Sung Li
IPC分类号： G01D5/24 , G01L9/12 , G01P15/125 , H04L27/06
CPC分类号： G01D5/24 , G01L9/12 , G01P15/125
摘要： Provided are a method and system for digitizing a sensor model output signal. The system includes a filter, a demodulator coupled to the filter, a DC offset cancellation mechanism coupled to the demodulator, and an analog to digital converter (ADC). The ADC is directly coupled to the demodulator and the DC offset cancellation mechanism.
摘要翻译：提供了一种用于数字化传感器模型输出信号的方法和系统。该系统包括滤波器，耦合到滤波器的解调器，耦合到解调器的DC偏移消除机构，以及模数转换器（ADC）。 ADC直接耦合到解调器和DC偏移消除机制。

8. 发明申请

US20070252745A1 Switching between lower and higher power modes in an ADC for lower/higher precision operations 有权
公开(公告)号：US20070252745A1
公开(公告)日：2007-11-01
申请号：US11824636
申请日：2007-06-29
申请人： Srinivasa Garlapati , Paul Lettieri , Jason Trachewsky , Gregory Efland , Tom Kwan
发明人： Srinivasa Garlapati , Paul Lettieri , Jason Trachewsky , Gregory Efland , Tom Kwan
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/0692 , H03M1/0695 , H03M1/167
摘要： An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inbound data is detected, at which time the ADC switches to a higher power-higher precision mode to convert the data. Once data conversion is completed, the ADC switches back to the lower power-lower precision mode to conserve power.

9. 发明申请

US20070077908A1 Fully integrated tuner architecture 有权
标题翻译：完全集成的调谐器架构
公开(公告)号：US20070077908A1
公开(公告)日：2007-04-05
申请号：US11393899
申请日：2006-03-31
申请人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher Ward , Ralph Duncan , Tom Kwan , James Chang , Haideh Khorramabadi
发明人： Pieter Vorenkamp , Klaas Bult , Frank Carr , Christopher Ward , Ralph Duncan , Tom Kwan , James Chang , Haideh Khorramabadi
IPC分类号： H04B1/10 , H04B1/26 , H04N5/455
CPC分类号： H03D3/18 , H01F17/0006 , H01F17/0013 , H01F27/34 , H01F27/40 , H01F27/42 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/04 , H03B5/364 , H03D7/161 , H03D7/18 , H03F1/26 , H03F1/3211 , H03F3/195 , H03F3/45183 , H03F3/45188 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/372 , H03F2200/447 , H03F2200/63 , H03F2203/45264 , H03F2203/45286 , H03G1/0023 , H03G1/0029 , H03G3/3052 , H03H7/25 , H03H11/04 , H03H11/1291 , H03H11/53 , H03H11/54 , H03H19/004 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/183 , H03L7/23 , H03L2207/06 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。

10. 发明申请

US20060202755A1 GIGABIT ETHERNET TRANSCEIVER WITH ANALOG FRONT END 有权
标题翻译：具有模拟前端的GIGABIT以太网收发器
公开(公告)号：US20060202755A1
公开(公告)日：2006-09-14
申请号：US11420406
申请日：2006-05-25
申请人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03F3/68
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal, By isolating the switches from the signal path linearity of the PGA can be improved.
摘要翻译：电路从集成电路可编程增益衰减器中的信号路径中去除开关可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。这种开关可能在信号中引入非线性。通过将开关与信号路径隔离，可以提高PGA的线性度。

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