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1. 发明授权

US07835387B2 Methods and systems for digitally processing data signals 有权
标题翻译：用于数字处理数据信号的方法和系统
公开(公告)号：US07835387B2
公开(公告)日：2010-11-16
申请号：US12496211
申请日：2009-07-01
申请人： Oscar Agazzi , Venugopal Gopinathan
发明人： Oscar Agazzi , Venugopal Gopinathan
IPC分类号： H04L12/66
CPC分类号： H04B10/6971 , H03M1/0604 , H03M1/0607 , H03M1/0624 , H03M1/0836 , H03M1/1215 , H04B10/6933 , H04B10/697 , H04L7/0062 , H04L25/03057 , H04L25/03159 , H04L2025/03445
摘要： Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal.
摘要翻译：用于接收电和/或光数据信号的基于数字信号处理的方法和系统包括电接收机，光接收机，并行接收机，多信道接收机，定时恢复方案，并且不限于均衡方案。本发明被实现为单路径接收机。或者，本发明被实现为多路径并行接收机，其中使用以较低速率操作的并行路径来实现模数转换器（“ADC”）和/或数字信号处理器（“DSP”）比接收的数据信号。

2. 发明申请

US20070047968A1 Method, Apparatus and System for High-Speed Transmission on Fiber Optic Channel 失效
标题翻译：光纤通道高速传输方法，装置及系统
公开(公告)号：US20070047968A1
公开(公告)日：2007-03-01
申请号：US11552452
申请日：2006-10-24
申请人： Oscar Agazzi
发明人： Oscar Agazzi
IPC分类号： H04B10/04
CPC分类号： H04L1/006 , H04B10/2575 , H04B10/2581 , H04B10/504 , H04B10/5055 , H04B10/541 , H04B10/548 , H04J14/02 , H04L25/0204 , H04L25/0224 , H04L27/2637 , H04L27/2653 , H04L27/2697 , H04L27/34
摘要： Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic channel. A receiver may then receive the laser signal from the fiber optic channel and convert it into an electrical signal. Multi-carrier modulation may be applied to existing fiber channels, which may be of lower quality. Existing fiber channels may have characteristics which prevent or restrict the transmission of data using intensity modulation at certain frequencies. An adaptive multi-carrier modulation transmitter may characterize an existing fiber optic channel and ascertain the overall characteristics of the channel. The transmitter and receiver can then be configured to use various bandwidths and various modulations in order to match the transfer characteristic of the fiber channel. A series of adaptive multi-carrier modulation transmitters and receivers can be integrated on a single integrated circuit. If multiple adaptive receivers and transmitters are integrated on a single integrated circuit, they may be used to upgrade existing networks by adding different wavelength lasers for the transmission of data in order to achieve any capacity desired. Each receiver and transmitter may characterize the fiber for its particular wavelength laser and may configure the modulation and bandpass to the fiber's characteristics.
摘要翻译：使用一系列电载体构建的多载波调制光纤系统，调制电载波上的数据并组合载波以形成宽带信号。然后可以在激光器上对宽带信号进行强度调制并耦合到光纤通道。然后，接收器可以从光纤通道接收激光信号并将其转换为电信号。多载波调制可以应用于可能具有较低质量的现有光纤信道。现有的光纤通道可以具有在某些频率下使用强度调制来防止或限制数据传输的特性。自适应多载波调制发射机可以表征现有光纤信道并确定信道的总体特性。然后可以将发射机和接收机配置为使用各种带宽和各种调制，以便匹配光纤信道的传输特性。一系列自适应多载波调制发射机和接收机可集成在单个集成电路上。如果多个自适应接收机和发射机集成在单个集成电路上，则它们可用于通过为数据传输添加不同波长的激光器来升级现有网络，以实现所需的任何容量。每个接收器和发射器可以表征其特定波长激光器的光纤，并且可以配置对光纤的特性的调制和带通。

3. 发明申请

US20060192614A1 Gigabit ethernet transceiver with analog front end 有权
公开(公告)号：US20060192614A1
公开(公告)日：2006-08-31
申请号：US11345946
申请日：2006-02-02
申请人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Arya Behzad , Klaas Bult , Ramon Gomez , Chi-Hung Lin , Tom Kwan , Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03B1/00
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

4. 发明申请

US20050036576A1 Multi-pair gigabit ethernet transceiver 有权
标题翻译：多对千兆以太网收发器
公开(公告)号：US20050036576A1
公开(公告)日：2005-02-17
申请号：US10919729
申请日：2004-08-17
申请人： Oscar Agazzi , John Creigh , Mehdi Hatamian , Henry Samueli , David Kruse , Arthur Abnous
发明人： Oscar Agazzi , John Creigh , Mehdi Hatamian , Henry Samueli , David Kruse , Arthur Abnous
IPC分类号： G01R31/30 , G01R31/317 , G01R31/3185 , H04B3/23 , H04B3/32 , H04L1/00 , H04L1/24 , H04L5/14 , H04L7/02 , H04L7/033 , H04L25/03 , H04L25/06 , H04L25/14 , H04L25/49 , H04L25/497 , H04L25/08
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

5. 发明授权

US4866739A Digital fast recovery timing algorithm 失效
标题翻译：数字快速恢复定时算法
公开(公告)号：US4866739A
公开(公告)日：1989-09-12
申请号：US158346
申请日：1988-02-22
申请人： Oscar Agazzi , Chris Cole , Steve Levy
发明人： Oscar Agazzi , Chris Cole , Steve Levy
IPC分类号： H04L7/02 , H04L7/033 , H04L27/38
CPC分类号： H04L7/007 , H04L27/38
摘要： The present invention employs a four sample per baud timing recovery scheme to achieve fast acquistion of initial timing phase uncertainity and reliable fast tracking with low jitter for non-equalized QAM wave forms. The present invention operates for data timing frequency uncertainties up to 0.02 percent in the preferred embodiment. The timing recovery system is implemented with programmable digital signal processor code in connection with a programmable phase baud timer. The baud timer may be implemented in software or hardware. The present scheme is based on a pair of quadrature (T/4 spaced) timing error signals derived by a wave difference method. In the wave difference method, the envelope power of each baud sample is computed by square summing the real and imaginary samples of the received analog signal.
摘要翻译：本发明采用每个波特率定时恢复方案的四个采样来实现初始定时相位不确定性的快速采集和用于非均衡QAM波形的低抖动的可靠快速跟踪。在优选实施例中，本发明用于高达0.02％的数据定时频率不确定性。定时恢复系统采用可编程数字信号处理器代码与可编程相位波特率定时器相结合。波特率定时器可以在软件或硬件中实现。本方案基于通过波差法导出的一对正交（T / 4间隔）定时误差信号。在波差方法中，每个波特率采样的包络功率通过对接收的模拟信号的实数和虚数样本进行平方和来计算。

6. 发明申请

US20090310665A1 Methods and Systems for Digitally Processing Optical Data Signals 有权
标题翻译：数字处理光数据信号的方法与系统
公开(公告)号：US20090310665A1
公开(公告)日：2009-12-17
申请号：US12496211
申请日：2009-07-01
申请人： Oscar Agazzi , Venugopal Gopinathan
发明人： Oscar Agazzi , Venugopal Gopinathan
IPC分类号： H04L27/06 , H03H7/40
CPC分类号： H04B10/6971 , H03M1/0604 , H03M1/0607 , H03M1/0624 , H03M1/0836 , H03M1/1215 , H04B10/6933 , H04B10/697 , H04L7/0062 , H04L25/03057 , H04L25/03159 , H04L2025/03445
摘要： Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal.
摘要翻译：用于接收电和/或光数据信号的基于数字信号处理的方法和系统包括电接收机，光接收机，并行接收机，多信道接收机，定时恢复方案，并且不限于均衡方案。本发明被实现为单路径接收机。或者，本发明被实现为多路径并行接收机，其中使用以较低速率操作的并行路径来实现模数转换器（“ADC”）和/或数字信号处理器（“DSP”）比接收的数据信号。

7. 发明申请

US20070242739A1 MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING A SINGLE-STATE DECISION FEEDBACK EQUALIZER 失效
标题翻译：具有单一状态决定反馈均衡器的多对智能电网收发器
公开(公告)号：US20070242739A1
公开(公告)日：2007-10-18
申请号：US11692091
申请日：2007-03-27
申请人： Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03H7/30
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

8. 发明申请

US20070183540A1 MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING ADAPTIVE DISABLING OF CIRCUIT ELEMENTS 有权
标题翻译：具有自适应电路元件的多对智能电网收发器
公开(公告)号：US20070183540A1
公开(公告)日：2007-08-09
申请号：US11688683
申请日：2007-03-20
申请人： Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar Agazzi , John Creigh , Mehdi Hatamian , David Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03D1/00 , H04B1/10
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

9. 发明授权

US07245638B2 Methods and systems for DSP-based receivers 有权
标题翻译：基于DSP的接收机的方法和系统
公开(公告)号：US07245638B2
公开(公告)日：2007-07-17
申请号：US10085071
申请日：2002-03-01
申请人： Oscar Agazzi , Venugopal Gopinathan
发明人： Oscar Agazzi , Venugopal Gopinathan
IPC分类号： H04J3/06
CPC分类号： H04L25/03006 , H03M1/0604 , H03M1/0607 , H03M1/0609 , H03M1/0624 , H03M1/0836 , H03M1/1215 , H04B10/6933 , H04B10/697 , H04B10/6971 , H04L7/0054 , H04L7/0062 , H04L7/0337 , H04L25/03057 , H04L25/03133 , H04L25/03159 , H04L25/03203 , H04L2025/03445
摘要： Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.
摘要翻译：用于接收数据信号的基于数字信号处理的方法和系统包括并行接收机，多信道接收机，定时恢复方案，并且不限于均衡方案。本发明被实现为多路径并行接收机，其中使用平行路径来实现模数转换器（“ADC”）和/或数字信号处理器（“DSP”），该路径以比接收数据信号。在一个实施例中，根据本发明的基于并行DSP的接收机包括用于每个ADC路径的单独的定时恢复环路。在一个实施例中，并行基于DSP的接收机包括用于每个ADC路径的单独的自动增益控制（AGC）环路。在一个实施例中，并行基于DSP的接收机包括用于每个ADC路径的单独的偏移补偿环路。在一个实施例中，本发明被实现为接收多个数据信号的多信道接收机。

10. 发明申请

US20070133722A1 Multi-Channel Equalization to Compensate for Impairments Introduced by Interleaved Devices 有权
标题翻译：多通道均衡补偿交错设备引入的损害
公开(公告)号：US20070133722A1
公开(公告)日：2007-06-14
申请号：US11538025
申请日：2006-10-02
申请人： Oscar Agazzi , Diego Crivelli , Hugo Carrer , Mario Hueda , German Luna
发明人： Oscar Agazzi , Diego Crivelli , Hugo Carrer , Mario Hueda , German Luna
IPC分类号： H03D1/04 , H03H7/30 , H03D1/00
CPC分类号： H04L25/03057 , H03M1/0626 , H03M1/1215 , H04L25/03184 , H04L25/03292 , H04L2025/03356 , H04L2025/03426 , H04L2025/03477 , H04L2025/03617
摘要： A system includes a time-interleaved device. An equalizer effectively can apply different equalization to different interleaved channels. For convenience, these equalizers will be referred to as multi-channel equalizers. In one aspect, an apparatus includes an interleaved device having M interleaved channels, and a multi-channel equalizer coupled to the interleaved device. The multi-channel equalizer is capable of applying a different equalization to different interleaved channels, thus compensating for channel-dependent impairments.
摘要翻译：系统包括时间交织设备。均衡器可以有效地将不同的均衡应用于不同的交织信道。为了方便起见，这些均衡器将被称为多通道均衡器。在一个方面，一种装置包括具有M个交织信道的交织设备和耦合到该交错设备的多信道均衡器。多信道均衡器能够对不同的交织信道应用不同的均衡，从而补偿信道相关损伤。

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