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1. 发明授权

US07158062B2 Clocked DAC current switch 有权
标题翻译：时钟DAC电流开关
公开(公告)号：US07158062B2
公开(公告)日：2007-01-02
申请号：US10761790
申请日：2004-01-21
申请人： Albert E. Cosand
发明人： Albert E. Cosand
IPC分类号： H03M3/00
CPC分类号： H03M3/376 , H03M3/464
摘要： A switch having a first arrangement for providing a first set of first and second complementary intermediate signals; a second arrangement for providing a second set of third and fourth complementary intermediate signals; a third arrangement responsive to the first set of signals for providing complementary output signals; a fourth arrangement responsive to the second set of signals for providing complementary output signals; and a fifth arrangement for selectively activating the third means or the fourth arrangement in response to a control signal.
摘要翻译：一种开关，具有用于提供第一组第一和第二互补中间信号的第一装置; 用于提供第二组第三和第四互补中间信号的第二装置; 响应于所述第一组信号以提供互补输出信号的第三装置; 响应于所述第二组信号以提供互补输出信号的第四布置; 以及响应于控制信号选择性地激活第三装置或第四装置的第五装置。

2. 发明授权

US5324997A Delayed negative feedback circuit 失效
标题翻译：延迟负反馈电路
公开(公告)号：US5324997A
公开(公告)日：1994-06-28
申请号：US21385
申请日：1993-02-23
申请人： Albert E. Cosand
发明人： Albert E. Cosand
IPC分类号： H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K19/013
摘要： A modification to the design of high speed logic circuitry will increase the speed of the circuitry. The modification consists of a delayed negative feedback added to the interface between two gates (a driving gate and a driven gate). The feedback is delayed by a time similar to the gate propagation delay, so that when a transition occurs, the feedback is effectively positive for times less than the feedback delay time. The effect of this is to add a bias at the interface that will aid the next transition of the driven gate during the transition. After a transition, the polarity of the bias is reversed so it will again aid the next transition.
摘要翻译：对高速逻辑电路设计的修改将提高电路的速度。修改包括添加到两个门（驱动门和从动门）之间的接口的延迟负反馈。反馈被延迟一个类似于门传播延迟的时间，所以当发生转变时，反馈对于小于反馈延迟时间的时间是有效的。这样做的结果是在界面处增加偏置，这将有助于在转换期间驱动栅极的下一个转换。在转变之后，偏置的极性反转，因此它将再次帮助下一个转换。

3. 发明授权

US5304951A Divider synchronization circuit for phase-locked loop frequency synthesizer 失效
标题翻译：锁相环频率合成器分频同步电路
公开(公告)号：US5304951A
公开(公告)日：1994-04-19
申请号：US829183
申请日：1992-01-31
申请人： Albert E. Cosand
发明人： Albert E. Cosand
IPC分类号： H03L7/18 , H03L7/189 , H03L7/199
CPC分类号： H03L7/199 , H03L7/189 , H03L2207/18
摘要： A divider synchronization circuit (11) that provides faster settling to a new frequency in a phase-locked loop frequency synthesizer (10) that uses a programmable divider (16) and a phase detector (17). The circuit (11) is adapted to stop the divider (16) while its program is being changed, and then restart the divider (16) on command. The startup time of the divider (16) is automatically adjusted such that the divider output is in phase with a reference input to a phase detector (17). The outputs of the phase detector (17) are also blanked during the time period that the divider (16) is stopped. The circuit (11) reduces the time required for the phase locked-loop frequency synthesizer (10) to settle to its new frequency and phase when the frequency is changed. The timing of the divider startup eliminates the large phase transient that may occur when the divider startup timing is random, thus shortening the time that must be allowed for the synthesizer output to settle to its final phase. This circuit (11) is of particular value in a fast settling synthesizer design in which a VCO is pretuned to a close approximation to the new output frequency and then the loop is closed to drive the frequency to its exact value. The circuit (11) is well adapted for use in spread spectrum and frequency-agile radar systems, or spread spectrum communications systems.
摘要翻译：一种分频器同步电路（11），其在使用可编程分频器（16）和相位检测器（17）的锁相环频率合成器（10）中提供更快的建立到新的频率。电路（11）适于在其程序改变时停止分频器（16），然后按命令重新启动分频器（16）。分频器（16）的启动时间被自动调节，使得分频器输出与与相位检测器（17）的基准输入同相。在除法器（16）停止的时间段期间，相位检测器（17）的输出也被消隐。当频率改变时，电路（11）减少锁相环频率合成器（10）在其新的频率和相位上所需的时间。分频器启动的时序消除了当分频器启动时序是随机时可能发生的大相位瞬变，从而缩短了合成器输出必须允许的时间才能稳定到其最后的相位。在快速稳定合成器设计中，该电路（11）具有特殊的价值，其中VCO被预先约束到近似于新的输出频率，然后闭环以将频率驱动到其精确值。电路（11）很好地适用于扩频和频率敏捷雷达系统或扩频通信系统。

4. 发明授权

US5729230A Delta-Sigma .DELTA.-.SIGMA. modulator having a dynamically tunable continuous time Gm-C architecture 失效
标题翻译：具有动态可调连续时间Gm-C架构的Delta-Sigma DELTA-SIGMA调制器
公开(公告)号：US5729230A
公开(公告)日：1998-03-17
申请号：US588666
申请日：1996-01-17
申请人： Joseph F. Jensen , Gopal Raghavan , Albert E. Cosand
发明人： Joseph F. Jensen , Gopal Raghavan , Albert E. Cosand
IPC分类号： H03M3/02 , H03M3/00
CPC分类号： H03M3/396 , H03M3/406 , H03M3/43 , H03M3/454
摘要： A continuous-time tunable Gm-C architecture for a .DELTA..SIGMA. modulator includes a tunable resonator and a low bit rate, high sample rate quantizer connected in a feedback loop. The resonator shapes the quantization noise spectrum so that the bulk of the quantization noise occurs outside the signal spectrum. A tunable Gm cell tunes the resonator's resonant frequency to maximize the modulator's SNR. The tunable Gm cell includes a fixed Gm cell having transconductance G.sub.f, a current divider and a recombination circuit that together effectively multiply G.sub.f by a factor .alpha., where -1
摘要翻译：用于DELTA SIGMA调制器的连续可调Gm-C架构包括可调谐谐振器和连接在反馈回路中的低比特率高采样率量化器。谐振器对量化噪声谱进行整形，使得量化噪声的大部分发生在信号谱外。可调谐Gm单元调谐谐振器的谐振频率以最大化调制器的SNR。可调谐Gm单元包括具有跨导Gf的固定Gm单元，分流器和复合电路，其一起有效地将Gf乘以因子α，其中-1 <=α<= 1，而不影响单元的共模电流Icm。正电流源提供Icm，同时保持R / 2的共模电阻和理论上无限差分模式电阻。因此，谐振器的谐振频率可以从DC变化到约1Ghz，同时保持稳定的共模工作点并改善调制器的品质因数。

5. 发明授权

US5726600A NPN bipolar circuit topology for a tunable transconductance cell and positive current source 失效
标题翻译：用于可调谐跨导电池和正电流源的NPN双极电路拓扑
公开(公告)号：US5726600A
公开(公告)日：1998-03-10
申请号：US588665
申请日：1996-01-17
申请人： Gopal Raghavan , Joseph F. Jensen , Albert E. Cosand
发明人： Gopal Raghavan , Joseph F. Jensen , Albert E. Cosand
IPC分类号： H03H11/04 , H03F3/45 , H03K5/22
CPC分类号： H03H11/0472 , H03H11/0444
摘要： An active filter circuit component includes an all NPN bipolar tunable Gm cell and a positive current source (PCS) for supplying common mode current. The tunable Gm cell includes a fixed Gm cell having transconductance G.sub.f, a current divider and recombination circuit that together effectively multiply G.sub.f by a tuning factor .alpha., where -1.ltoreq..alpha..ltoreq.1, without effecting the cell's common mode current I.sub.cm. The PCS includes a pair of unity gain inverting single ended amplifiers that are connected in antiparallel across a pair of matched resistors. Alternately, the resistors can be connected across the inverting and non-inverting sides of a differential amplifier. A constant voltage is applied across the resistors to supply I.sub.cm, while maintaining a common mode resistance of R/2 and a differential mode resistance approaching infinity.
摘要翻译：有源滤波器电路组件包括用于提供共模电流的全NPN双极可调谐Gm单元和正电流源（PCS）。可调谐Gm单元包括具有跨导Gf的固定Gm单元，电流分配器和复合电路，其一起有效地将Gf乘以调谐因子α，其中-1 <=α<1，而不影响单元的共模电流Icm 。 PCS包括一对在一对匹配电阻器上反并联连接的单位增益反相单端放大器。或者，电阻器可以跨差分放大器的反相和非反相侧连接。在电阻之间施加恒定电压以提供Icm，同时保持R / 2的共模电阻和接近无限远的差模电阻。

6. 发明授权

US07940201B1 Photonic analog to digital converter input sampler 有权
标题翻译：光子模数转换器输入采样器
公开(公告)号：US07940201B1
公开(公告)日：2011-05-10
申请号：US12497448
申请日：2009-07-02
申请人： Albert E. Cosand
发明人： Albert E. Cosand
IPC分类号： H03M1/00
CPC分类号： H03M1/1255
摘要： An input sampler interface to a track and hold circuit that decouples a high bandwidth (possibly optical domain) input signal from a lower bandwidth electrical domain of a subsequent track and hold circuit or other circuit.
摘要翻译：与轨道和保持电路的输入采样器接口，其将高带宽（可能的光域）输入信号与随后的跟踪和保持电路或其他电路的较低带宽电域分离。

7. 发明授权

US4975931A High speed programmable divider 失效
标题翻译：高速可编程分频器
公开(公告)号：US4975931A
公开(公告)日：1990-12-04
申请号：US286435
申请日：1988-12-19
申请人： Albert E. Cosand
发明人： Albert E. Cosand
IPC分类号： H03K23/64 , H03K21/10 , H03K23/66 , H03K23/68
CPC分类号： H03K23/665 , H03K21/10 , H03K23/667 , H03K23/68
摘要： A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmable divider and the programmable divider utilizes the multiple clock phases to allow operation in a true fractional-integer mode. The overall combination of the prescaler and programmable divider functions as a programmable divider for which the minimum increment in the overall divider modulus is less than the prescaler modulus, but the maximum clock frequency usable is the maximum clock frequency of the prescaler.
摘要翻译：可编程计数器或分频器包括固定模数预分频器（110）和可编程分频器（120,130,140,150,160）的组合，其中预分频器向可编程分频器提供多于单个时钟相位，并且可编程分频器分频器利用多个时钟相位允许以真正的分数整数模式运行。预分频器和可编程分频器的总体组合功能用作可编程分频器，其中总分频器模数的最小增量小于预分频器模数，但可用的最大时钟频率是预分频器的最大时钟频率。

8. 发明授权

US08207782B1 Circuits and methods to minimize thermally generated offset voltages 有权
标题翻译：减少热产生的偏移电压的电路和方法
公开(公告)号：US08207782B1
公开(公告)日：2012-06-26
申请号：US13038202
申请日：2011-03-01
申请人： Albert E. Cosand
发明人： Albert E. Cosand
IPC分类号： H01L35/00
CPC分类号： H03F1/302 , H03F1/0277 , H03F1/526 , H03F3/45085 , H03F3/72 , H03F2200/447 , H03F2203/45366 , H03F2203/45466 , H03F2203/45511
摘要： A circuit to minimize thermally generated offset voltages includes a differential pair of transistors having a first transistor and a second transistor and coupled to a current source, a differential input having a first input coupled to the first transistor and having a second input coupled to the second transistor, a pair of bypass transistors having a first bypass transistor and a second bypass transistor, the first bypass transistor coupled in parallel with the first transistor and the second bypass transistor coupled in parallel with the second transistor, wherein the pair of bypass transistors is coupled to the current source, and control circuitry coupled to the pair of bypass transistors for controlling current through the pair of bypass transistors.
摘要翻译：用于最小化热产生的偏移电压的电路包括具有第一晶体管和第二晶体管并耦合到电流源的差分对晶体管，差分输入具有耦合到第一晶体管的第一输入端，并具有耦合到第二晶体管的第二输入端晶体管，一对具有第一旁路晶体管和第二旁路晶体管的旁路晶体管，所述第一旁路晶体管与所述第一晶体管并联耦合，所述第二旁路晶体管与所述第二晶体管并联耦合，其中所述一对旁路晶体管被耦合以及耦合到该对旁路晶体管的控制电路，用于控制通过一对旁路晶体管的电流。

9. 发明授权

US08050644B1 Highly linear mixer and method for cancelling FET channel resistance modulation 有权
标题翻译：高线性混频器和消除FET沟道电阻调制的方法
公开(公告)号：US08050644B1
公开(公告)日：2011-11-01
申请号：US12337379
申请日：2008-12-17
申请人： Albert E. Cosand , Joseph F. Jensen
发明人： Albert E. Cosand , Joseph F. Jensen
IPC分类号： H04B1/10
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D2200/0023 , H03D2200/0043 , H03D2200/0088 , H04B15/06
摘要： A highly linear mixer and method for cancelling field effect transistor channel resistance modulation are provided. At least a portion of the voltage of an input signal is added to a drive signal to cancel distortion arising from modulation of the voltage of the input signal.
摘要翻译：提供一种用于消除场效应晶体管沟道电阻调制的高线性混频器和方法。将输入信号的电压的至少一部分加到驱动信号上，以消除由调制输入信号的电压引起的失真。

10. 发明授权

US07948297B1 Circuits and methods to minimize thermally generated offset voltages 有权
标题翻译：减少热产生的偏移电压的电路和方法
公开(公告)号：US07948297B1
公开(公告)日：2011-05-24
申请号：US12272533
申请日：2008-11-17
申请人： Albert E. Cosand
发明人： Albert E. Cosand
IPC分类号： H01L37/00
CPC分类号： H03F1/302 , H03F1/0277 , H03F1/526 , H03F3/45085 , H03F3/72 , H03F2200/447 , H03F2203/45366 , H03F2203/45466 , H03F2203/45511
摘要： A circuit to minimize thermally generated offset voltages includes a differential pair of transistors having a first transistor and a second transistor and coupled to a current source, a differential input having a first input coupled to the first transistor and having a second input coupled to the second transistor, a pair of bypass transistors having a first bypass transistor and a second bypass transistor, the first bypass transistor coupled in parallel with the first transistor and the second bypass transistor coupled in parallel with the second transistor, wherein the pair of bypass transistors is coupled to the current source, and control circuitry coupled to the pair of bypass transistors for controlling current through the pair of bypass transistors.
摘要翻译：用于最小化热产生的偏移电压的电路包括具有第一晶体管和第二晶体管并耦合到电流源的差分对晶体管，差分输入具有耦合到第一晶体管的第一输入端，并具有耦合到第二晶体管的第二输入端晶体管，一对具有第一旁路晶体管和第二旁路晶体管的旁路晶体管，所述第一旁路晶体管与所述第一晶体管并联耦合，所述第二旁路晶体管与所述第二晶体管并联耦合，其中所述一对旁路晶体管被耦合以及耦合到该对旁路晶体管的控制电路，用于控制通过一对旁路晶体管的电流。

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