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    • 1. 发明授权
    • Wake-on-frame for frame processing devices
    • 帧处理设备的唤醒功能
    • US09229518B1
    • 2016-01-05
    • US12916968
    • 2010-11-01
    • Donald PannellHong Yu Chou
    • Donald PannellHong Yu Chou
    • G06F1/32
    • G06F1/3203G06F1/3209G06F1/3287
    • Systems, methods, and other embodiments associated with wake-on-frame mechanisms are described. According to one embodiment, an apparatus includes a packet source configured to send packets to a frame processing device and a wake-on-frame mechanism that is selectable by the frame processing device between an enabled state and a disabled state. If the wake-on-frame mechanism is in the enabled state, a packet source that has a frame to send to the frame processing device sends a wake signal to the frame processing device prior to sending the packet. The packet source sends the packet to the frame processing device after receiving a ready signal from the frame processing device.
    • 描述了与唤醒帧机制相关联的系统,方法和其他实施例。 根据一个实施例,一种装置包括被配置为向帧处理设备发送分组的分组源和在启用状态和禁用状态之间可由帧处理设备选择的唤醒帧机制。 如果唤醒帧机制处于使能状态,则具有要发送到帧处理设备的帧的分组源在发送分组之前向帧处理设备发送唤醒信号。 在从帧处理设备接收到就绪信号之后,分组源将该分组发送到帧处理设备。
    • 5. 发明授权
    • Inter-device flow control
    • 设备间流量控制
    • US07680053B1
    • 2010-03-16
    • US11254588
    • 2005-10-20
    • Donald PannellHong Yu Chou
    • Donald PannellHong Yu Chou
    • H04L12/26
    • H04L47/10H04L47/26H04L49/506
    • A network switching device comprises first and second ports. A queue communicates with the second port, stores frames for later output by the second port, and generates a congestion signal when filled above a threshold. A control module selectively sends an outgoing flow control message to the first port when the congestion signal is present, and selectively instructs the second port to assert flow control when a flow control message is received from the first port if the received flow control message designates the second port as a target.
    • 网络交换设备包括第一和第二端口。 队列与第二端口通信,存储帧以供稍后由第二端口输出,并且当填充在阈值以上时产生拥塞信号。 当拥塞信号存在时,控制模块选择性地向第一端口发送流出控制消息,并且如果接收的流量控制消息指定了从第一端口接收到流控制消息,则有选择地指示第二端口断言流量控制 第二个港口作为目标。
    • 7. 发明授权
    • Remote management for network switches
    • 网络交换机的远程管理
    • US07876746B1
    • 2011-01-25
    • US11810667
    • 2007-06-06
    • Donald PannellHong Yu Chou
    • Donald PannellHong Yu Chou
    • H04L12/66H04L12/50H04Q11/00
    • H04L41/26H04L41/24H04Q3/0062
    • An apparatus includes at least one input circuit to receive frames of data, the frames of data comprising first frames each having first data, and a second frame having second data. The apparatus includes at least one output circuit to transmit the first frames; a forwarding engine to transfer the first frames from the at least one input circuit to the at least one output circuit; and a first memory to store switch information. The apparatus operates according to the switch information. The at least one input circuit includes a remote management unit comprising a first memory controller to modify the switch information stored in the first memory according to the second data in the second frame, and a second memory; a second memory controller to write each of the frames of data to the second memory; and a remote management enable circuit to enable the remote management unit when the second frame is a remote management frame. The first memory controller writes the second data from the second memory to the first memory when the remote management unit is enabled by the remote management enable circuit and the remote management frame includes a valid write command.
    • 一种装置包括至少一个用于接收数据帧的输入电路,所述数据帧包括每个具有第一数据的第一帧,以及具有第二数据的第二帧。 该装置包括至少一个用于传输第一帧的输出电路; 转发引擎,用于将所述第一帧从所述至少一个输入电路传送到所述至少一个输出电路; 以及存储交换机信息的第一存储器。 该设备根据交换机信息进行操作。 所述至少一个输入电路包括远程管理单元,所述远程管理单元包括第一存储器控制器,用于根据第二帧中的第二数据修改存储在第一存储器中的开关信息,以及第二存储器; 第二存储器控制器,用于将每个数据帧写入第二存储器; 以及远程管理启用电路,用于当所述第二帧是远程管理帧时使所述远程管理单元能够启用。 当远程管理单元由远程管理启用电路启用并且远程管理帧包括有效的写命令时,第一存储器控制器将第二数据从第二存储器写入第一存储器。
    • 8. 发明授权
    • Enhanced audio video bridging (AVB) methods and apparatus
    • 增强音视频桥接(AVB)方法和设备
    • US09584342B1
    • 2017-02-28
    • US13115868
    • 2011-05-25
    • Donald Pannell
    • Donald Pannell
    • H04L12/46H04L12/54H04L12/913
    • H04L49/354H04J3/16H04L12/28H04L12/462H04L12/56H04L45/745H04L45/7453H04L47/24H04L47/2408H04L47/245H04L47/2458H04L47/6215H04L47/70H04L47/724H04L49/201H04L49/3027H04L49/90H04L2012/5638
    • A packet is received via a port of the network device, and a database lookup is performed using header information of the packet. A priority associated with the packet is determined, and it is determined whether the priority is associated with a particular communication protocol that provides guaranteed delivery, defined latency, and/or defined throughput. When it is determined that the priority is associated with the particular communication protocol, i) it is determined, based on the database lookup, whether a destination address (DA) of the packet is associated with the particular communication protocol, and ii) when it is determined that the DA of the packet is associated with the particular communication protocol, the packet is prevented from egressing from ports of the network device that are operating according to the particular communication protocol with a frame priority indicator corresponding to a value reserved for the particular communication protocol.
    • 通过网络设备的端口接收分组,并且使用分组的报头信息来执行数据库查找。 确定与分组相关联的优先级,并且确定优先级是否与提供保证传递,定义的等待时间和/或定义的吞吐量的特定通信协议相关联。 当确定优先级与特定通信协议相关联时,i)基于数据库查找确定分组的目的地地址(DA)是否与特定通信协议相关联,以及ii)何时 确定分组的DA与特定通信协议相关联,防止分组从根据特定通信协议操作的网络设备的端口出来,其中帧优先级指示符对应于为特定通信协议保留的值 通讯协议。
    • 9. 发明授权
    • Duplex mismatch detection
    • 双工不匹配检测
    • US08705416B2
    • 2014-04-22
    • US13315800
    • 2011-12-09
    • Donald PannellOzdal Barkan
    • Donald PannellOzdal Barkan
    • H04B1/44
    • H04L5/14
    • An apparatus including a port to transmit first frames and receive second frames over a communication channel, the port including a collision detect circuit and a duplex mismatch circuit. The collision detect circuit detects collisions on the communication channel between the first frames and the second frames. The duplex mismatch circuit declares a duplex mismatch when the communication channel was established without attempting auto-negotiation, the port is in a half-duplex mode, and the collision detect circuit detects a very late collision involving one of the first frames. The very late collision occurs after a predetermined amount of data has been transmitted in the one of the first frames. The duplex mismatch indicates that a full-duplex mode is used with respect to the second frames.
    • 一种装置,包括用于发送第一帧并通过通信信道接收第二帧的端口,所述端口包括冲突检测电路和双工不匹配电路。 冲突检测电路检测第一帧和第二帧之间的通信信道上的冲突。 当通信信道建立而不尝试自动协商,端口处于半双工模式,并且冲突检测电路检测到涉及其中一个第一帧的非常晚的冲突时,双工不匹配电路声明双工不匹配。 在第一帧之一中发送预定量的数据之后发生非常晚的冲突。 双工不匹配表示相对于第二帧使用全双工模式。
    • 10. 发明授权
    • Multiport memory architecture, devices and systems including the same, and methods of using the same
    • 多端口存储器架构,包括相同的器件和系统以及使用它们的方法
    • US08335878B2
    • 2012-12-18
    • US12494076
    • 2009-06-29
    • Winston LeeSehat SutardjaDonald Pannell
    • Winston LeeSehat SutardjaDonald Pannell
    • G06F7/00G11C11/401
    • G11C7/1075
    • A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.
    • 多端口内存架构,系统包括相同以及使用方法。 架构通常包括(a)存储器阵列; (b)配置成接收和/或发送数据的多个端口; 以及(c)多个端口缓冲器,每个端口缓冲器被配置为从一个或多个端口发送数据和/或从一个或多个端口接收数据,并且所有端口缓冲器被配置为(i)将数据发送到存储器 阵列在第一公共总线上,(ii)在第二公共总线上从存储器阵列接收数据。 系统通常包括体现本文公开的一个或多个发明构思的系统。 所述方法通常涉及将数据块写入到数据块,从存储器读取数据块和/或传送数据块。 本发明有利地通过将端口缓冲器紧密地耦合到主存储器并且有利地使用存储器读写路径的长段上的点对点通信来减少数据通信中的特别是网络交换机中的等待时间,从而减少路由拥塞和启用 消除FIFO。 本发明有利地缩小芯片尺寸并提供增加的数据传输速率和吞吐量,并且在优选实施例中,存储器读和写总线中的电阻和/或电容减小。