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1. 发明申请

US20090013022A1 Multiplier Engine Apparatus and Method 失效
标题翻译：乘法器发动机装置及方法
公开(公告)号：US20090013022A1
公开(公告)日：2009-01-08
申请号：US11773558
申请日：2007-07-05
申请人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
发明人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
IPC分类号： G06F7/523
CPC分类号： G06F7/5338 , G06F7/5318
摘要： A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bit 0 position.
摘要翻译：提供了减少用于提供乘法器引擎的电路的大小以及增加执行乘法算法的速度的乘法器引擎。示例性实施例可以包括具有一个或多个仅包括两个全加器的4：2压缩机的M * 8乘法引擎，与已知的5：2基于压缩机的架构中的三个全加器相反。 4：2压缩机能够通过使用部分乘积输入的最不重要部分中的未使用位来存储否定位值来实现与已知的5：2基于压缩器的架构相同的操作。此外，与部分积输入不融合的否定位值可以输入到位0位置的4：2压缩器。

2. 发明授权

US07958180B2 Multiplier engine 失效
标题翻译：乘法引擎
公开(公告)号：US07958180B2
公开(公告)日：2011-06-07
申请号：US11773558
申请日：2007-07-05
申请人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
发明人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/5318
摘要： A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bit 0 position.
摘要翻译：提供了减少用于提供乘法器引擎的电路的大小以及增加执行乘法算法的速度的乘法器引擎。示例性实施例可以包括具有一个或多个仅包括两个全加器的4：2压缩机的M * 8乘法引擎，与已知的5：2基于压缩机的架构中的三个全加器相反。 4：2压缩机能够通过使用部分乘积输入的最不重要部分中的未使用位来存储否定位值来实现与已知的5：2基于压缩器的架构相同的操作。此外，与部分积输入不融合的否定位值可以输入到位0位置的4：2压缩器。

3. 发明授权

US07797364B2 Booth decoder apparatus and method 失效
标题翻译：展位解码装置及方法
公开(公告)号：US07797364B2
公开(公告)日：2010-09-14
申请号：US11426652
申请日：2006-06-27
申请人： Owen Chiang
发明人： Owen Chiang
IPC分类号： G06F7/52
CPC分类号： G06F7/5338
摘要： A Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to generate an invert control signal output. The first and second circuits receive the three-bit block as an input and generate their respective outputs based on the setting of each of the bits. The third circuit receives only the most significant bit of the three-bit block as its input and generates an invert signal output based on the setting of the most significant bit. In each of these circuits, the number of complex gates and transistors is minimized thereby reducing gate delay and power consumption in generating the control signals for performing a Booth multiplication operation.
摘要翻译：展位解码器可以包括并行运行的三个电路。第一电路用于产生移位控制信号输出。第二个电路用于产生零控制信号输出。第三电路用于产生反相控制信号输出。第一和第二电路接收三位块作为输入，并根据每个位的设置生成其各自的输出。第三电路仅接收三位块的最高有效位作为其输入，并且基于最高有效位的设置产生反相信号输出。在这些电路中的每一个中，复合栅极和晶体管的数量被最小化，从而在产生用于执行布斯乘法运算的控制信号中减少门延迟和功耗。

4. 发明授权

US07693701B2 Structure for a configurable low power high fan-in multiplexer 失效
标题翻译：可配置低功耗高风扇多路复用器的结构
公开(公告)号：US07693701B2
公开(公告)日：2010-04-06
申请号：US12132501
申请日：2008-06-03
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： G06F17/50 , H03K19/094
CPC分类号： H03K17/005 , H03K19/0008
摘要： A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高扇入多路复用器（MUX）及其设计结构。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

5. 发明授权

US07466164B1 Method and apparatus for a configurable low power high fan-in multiplexer 有权
标题翻译：用于可配置低功率高风扇多路复用器的方法和装置
公开(公告)号：US07466164B1
公开(公告)日：2008-12-16
申请号：US11759426
申请日：2007-06-07
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/94
CPC分类号： H03K19/0008 , H03K17/005
摘要： A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高风扇多路复用器（MUX）。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

6. 发明授权

US07633316B2 Transmission gate multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US07633316B2
公开(公告)日：2009-12-15
申请号：US12256582
申请日：2008-10-23
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

7. 发明授权

US07605612B1 Techniques for reducing power requirements of an integrated circuit 失效
标题翻译：降低集成电路功耗要求的技术
公开(公告)号：US07605612B1
公开(公告)日：2009-10-20
申请号：US12121827
申请日：2008-05-16
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Daniel L. Stasiak , Albert J. Van Norstrand, Jr.
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Daniel L. Stasiak , Albert J. Van Norstrand, Jr.
IPC分类号： H03K19/00
CPC分类号： H03K19/0016 , G06F1/3203 , G06F1/3237 , G06F17/505 , G06F2217/78 , G06F2217/84 , Y02D10/128
摘要： A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value. Based on a current state of the control state machine, a load signal is provided to the counting circuit to cause the counting circuit to load an associated one of the first, second, and third values from the control register.
摘要翻译：时钟选通集成电路的时钟域的技术包括将第一，第二和第三值存储在控制寄存器中。第一值对应于在启动时钟门控之前等待的第一数量的时钟周期，第二值对应于执行时钟门控的第二数量的时钟周期，并且第三值对应于第三数量的时钟周期，其中不执行时钟门控。第一，第二和第三值之一被选择性地从控制寄存器加载到计数电路中。计数电路从加载的第一，第二和第三值之一计数到转换值。在控制状态机（从计数电路）接收到比较信号，指示计数电路已经达到转换值。基于控制状态机的当前状态，向计数电路提供负载信号，使得计数电路从控制寄存器加载相关的第一，第二和第三值中的一个。

8. 发明申请

US20080222227A1 Design Structure for a Booth Decoder 失效
标题翻译：展位解码器的设计结构
公开(公告)号：US20080222227A1
公开(公告)日：2008-09-11
申请号：US12127064
申请日：2008-05-27
申请人： Owen Chiang
发明人： Owen Chiang
IPC分类号： G06F7/533 , G06F17/10 , G06F7/57 , G06F17/50
CPC分类号： G06F7/5338
摘要： A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to generate an invert control signal output. The first and second circuits receive the three-bit block as an input and generate their respective outputs based on the setting of each of the bits. The third circuit receives only the most significant bit of the three-bit block as its input and generates an invert signal output based on the setting of the most significant bit. In each of these circuits, the number of complex gates and transistors is minimized thereby reducing gate delay and power consumption in generating the control signals for performing a Booth multiplication operation.
摘要翻译：提供了一种布斯解码器的设计结构。布斯解码器可以包括并行运行的三个电路。第一电路用于产生移位控制信号输出。第二个电路用于产生零控制信号输出。第三电路用于产生反相控制信号输出。第一和第二电路接收三位块作为输入，并根据每个位的设置生成其各自的输出。第三电路仅接收三位块的最高有效位作为其输入，并且基于最高有效位的设置产生反相信号输出。在这些电路中的每一个中，复合栅极和晶体管的数量被最小化，从而在产生用于执行布斯乘法运算的控制信号中减少门延迟和功耗。

9. 发明申请

US20090096486A1 Structure for Transmission Gate Multiplexer 审中-公开
标题翻译：传输门复用器的结构
公开(公告)号：US20090096486A1
公开(公告)日：2009-04-16
申请号：US12028940
申请日：2008-02-11
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/005
摘要： A technique and design structure for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术和设计结构包括从多个传输门组中选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

10. 发明授权

US07466165B1 Transmission gate multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US07466165B1
公开(公告)日：2008-12-16
申请号：US11854604
申请日：2007-09-13
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

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