专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090013022A1 Multiplier Engine Apparatus and Method 失效
标题翻译：乘法器发动机装置及方法
公开(公告)号：US20090013022A1
公开(公告)日：2009-01-08
申请号：US11773558
申请日：2007-07-05
申请人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
发明人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
IPC分类号： G06F7/523
CPC分类号： G06F7/5338 , G06F7/5318
摘要： A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bit 0 position.
摘要翻译：提供了减少用于提供乘法器引擎的电路的大小以及增加执行乘法算法的速度的乘法器引擎。示例性实施例可以包括具有一个或多个仅包括两个全加器的4：2压缩机的M * 8乘法引擎，与已知的5：2基于压缩机的架构中的三个全加器相反。 4：2压缩机能够通过使用部分乘积输入的最不重要部分中的未使用位来存储否定位值来实现与已知的5：2基于压缩器的架构相同的操作。此外，与部分积输入不融合的否定位值可以输入到位0位置的4：2压缩器。

2. 发明授权

US07958180B2 Multiplier engine 失效
标题翻译：乘法引擎
公开(公告)号：US07958180B2
公开(公告)日：2011-06-07
申请号：US11773558
申请日：2007-07-05
申请人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
发明人： Douglas H. Bradley , Owen Chiang , Sherman M. Dance
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/5318
摘要： A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bit 0 position.
摘要翻译：提供了减少用于提供乘法器引擎的电路的大小以及增加执行乘法算法的速度的乘法器引擎。示例性实施例可以包括具有一个或多个仅包括两个全加器的4：2压缩机的M * 8乘法引擎，与已知的5：2基于压缩机的架构中的三个全加器相反。 4：2压缩机能够通过使用部分乘积输入的最不重要部分中的未使用位来存储否定位值来实现与已知的5：2基于压缩器的架构相同的操作。此外，与部分积输入不融合的否定位值可以输入到位0位置的4：2压缩器。

3. 发明授权

US07716264B2 Method and apparatus for performing alignment shifting in a floating-point unit 有权
标题翻译：用于在浮点单元中执行对准移位的方法和装置
公开(公告)号：US07716264B2
公开(公告)日：2010-05-11
申请号：US11205987
申请日：2005-08-16
申请人： Sherman M. Dance , Jeffrey R. Summers , Shivakumar Swaminathan
发明人： Sherman M. Dance , Jeffrey R. Summers , Shivakumar Swaminathan
IPC分类号： G06F15/00
CPC分类号： G06F5/01
摘要： An apparatus for performing alignment shifting in a floating-point unit is disclosed. An alignment shifter includes a shift amount calculator, a set of first level shifters and a set of second level shifter. The shift amount calculator generates one shift amount under a double-precision mode and two shift amounts under a single-precision mode. The first level shifters can concurrently receive two double-precision mantissas under the double-precision mode or two single-precision mantissas under the single-precision mode. The first level of shifts performs small shifts concurrently on the two double-precision mantissas according to the single shift amount, or on the two single-precision mantissas according to the two shift amounts. The second level shifters performs large shifts on outputs from the first level shifters to generate one double-precision floating-point result or two single-precision floating-point results.
摘要翻译：公开了一种用于在浮点单元中进行对准移位的装置。对准移位器包括移位量计算器，一组第一电平移位器和一组第二电平移位器。移位量计算器在双精度模式下产生一个移位量，并在单精度模式下产生两个移位量。第一级移位器可以在双精度模式下同时接收两个双精度尾数，或者在单精度模式下同时接收两个单精度尾数。第一级别的换档根据单位移量在两个双精度尾数上同时执行小移动，或者根据两个移位量在两个单精度尾数上同时进行。第二电平移位器对来自第一电平移位器的输出执行大的移位，以产生一个双精度浮点运算或两个单精度浮点运算结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式