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1. 发明授权

US07843039B2 Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit 有权
标题翻译：应力改进的器件结构，制造这种应力改进的器件结构的方法以及集成电路的设计结构
公开(公告)号：US07843039B2
公开(公告)日：2010-11-30
申请号：US12030917
申请日：2008-02-14
申请人： Edward C. Cooney, III , Mark Dupuis , William J. Murphy , Steven S. Williams
发明人： Edward C. Cooney, III , Mark Dupuis , William J. Murphy , Steven S. Williams
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/732 , H01L21/76224 , H01L21/76843 , H01L21/8222 , H01L21/8228 , H01L27/0825 , H01L27/0826 , H01L29/0649 , H01L29/456
摘要： Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices. The intervening materials or structures, such as contacts extending through an insulating layer of a local interconnect level between the contact level and the semiconductor devices, provide paths for the transfer of stress from the stress-imparting structures to the stress-modified semiconductor devices.
摘要翻译：应力改进的器件结构，制造这种应力改进的器件结构的方法以及集成电路的设计结构。形成在公共衬底上的半导体器件的电特性，例如双极结晶体管的电流增益，可以通过间接地或间接地与半导体器件耦合的结构中的应力来改变。在互连的接触电平中可以为触点的衬垫的结构物理上与相应的半导体器件隔开距离并且不与其直接物理接触，因为至少一个附加的介入材料或结构位于应力 - 赋予结构和应力改进的装置。中间的材料或结构，例如延伸穿过接触层和半导体器件之间的局部互连层的绝缘层的触点，提供了将应力从应力赋予结构转移到应力改性半导体器件的路径。

2. 发明申请

US20090206449A1 STRESS-MODIFIED DEVICE STRUCTURES, METHODS OF FABRICATING SUCH STRESS-MODIFIED DEVICE STRUCTURES, AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT 有权
标题翻译：应变修正装置结构，制造这种应变修正装置结构的方法，以及集成电路的设计结构
公开(公告)号：US20090206449A1
公开(公告)日：2009-08-20
申请号：US12030917
申请日：2008-02-14
申请人： Edward C. Cooney III , Mark Dupuis , William J. Murphy , Steven S. Williams
发明人： Edward C. Cooney III , Mark Dupuis , William J. Murphy , Steven S. Williams
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/732 , H01L21/76224 , H01L21/76843 , H01L21/8222 , H01L21/8228 , H01L27/0825 , H01L27/0826 , H01L29/0649 , H01L29/456
摘要： Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices. The intervening materials or structures, such as contacts extending through an insulating layer of a local interconnect level between the contact level and the semiconductor devices, provide paths for the transfer of stress from the stress-imparting structures to the stress-modified semiconductor devices.
摘要翻译：应力改进的器件结构，制造这种应力改进的器件结构的方法以及集成电路的设计结构。形成在公共衬底上的半导体器件的电特性，例如双极结晶体管的电流增益，可以通过间接地或间接地与半导体器件耦合的结构中的应力来改变。在互连的接触电平中可以为触点的衬垫的结构物理上与相应的半导体器件隔开距离并且不与其直接物理接触，因为至少一个附加的介入材料或结构位于应力 - 赋予结构和应力改进的装置。中间的材料或结构，例如延伸穿过接触层和半导体器件之间的局部互连层的绝缘层的触点，提供用于将应力从应力赋予结构转移到应力改变的半导体器件的路径。

3. 发明授权

US08969195B2 Methods of manufacturing semiconductor devices and a semiconductor structure 有权
标题翻译：制造半导体器件和半导体结构的方法
公开(公告)号：US08969195B2
公开(公告)日：2015-03-03
申请号：US12035449
申请日：2008-02-22
申请人： Felix P. Anderson , Steven P. Barkyoumb , Edward C. Cooney, III , Thomas L. McDevitt , William J. Murphy , David C. Strippe
发明人： Felix P. Anderson , Steven P. Barkyoumb , Edward C. Cooney, III , Thomas L. McDevitt , William J. Murphy , David C. Strippe
IPC分类号： H01L21/44 , H01L21/285 , C23C14/02 , C23C14/06 , H01L21/768
CPC分类号： H01L23/53209 , C23C14/02 , C23C14/0641 , H01L21/2855 , H01L21/76843 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.
摘要翻译：提供了用于改善膜对半导体晶片和半导体结构的附着力的方法。通过实施本发明的方法，可以在晶片制造工艺期间显着抑制缺陷产生，例如减少颗粒产生。更具体地，所描述的工艺通过有效地增加TaN膜在晶片上的粘合性能，显着地减少了晶片的边缘或边缘（斜面）对TaN膜的剥落。在阻挡层制造过程中，相对于总钽加氮化物将氮化物的摩尔百分数提高到25％或更大的方法。

4. 发明授权

US07879716B2 Metal seed layer deposition 有权
标题翻译：金属种子层沉积
公开(公告)号：US07879716B2
公开(公告)日：2011-02-01
申请号：US11687017
申请日：2007-03-16
申请人： Steven P. Barkyoumb , Jonathan D. Chapple-Sokol , Edward C. Cooney, III , Keith E. Downes , Thomas L. McDevitt , William J. Murphy
发明人： Steven P. Barkyoumb , Jonathan D. Chapple-Sokol , Edward C. Cooney, III , Keith E. Downes , Thomas L. McDevitt , William J. Murphy
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76856 , H01L21/76859 , H01L21/76861 , H01L21/76862 , H01L21/76871 , H01L21/76873
摘要： A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.
摘要翻译：一种用于在半导体结构的制造过程中减少铜籽晶层的腐蚀的方法和结构。在结构（或包含结构的晶片）离开溅射工具的真空环境之前，将结构加热到高于溅射工具外部环境的水冷凝温度的温度。结果，当结构离开溅射工具时，水蒸气不会在结构上冷凝，因此防止了水蒸气对种子层的腐蚀。或者，在结构离开溅射工具环境之前，可以在籽晶层的顶部形成耐水蒸汽的保护层。在另一替代实施例中，种子层可以包括铜合金（例如用铝），其在暴露于水蒸汽时生长出耐水蒸气的保护层。

5. 发明授权

US06534394B1 Process to create robust contacts and interconnects 失效
标题翻译：创建稳健的联系人和互连的过程
公开(公告)号：US06534394B1
公开(公告)日：2003-03-18
申请号：US09660711
申请日：2000-09-13
申请人： Edward C. Cooney, III , William J. Murphy
发明人： Edward C. Cooney, III , William J. Murphy
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76846 , H01L21/76862 , H01L21/76865
摘要： A method is provided to preferably create robust contacts and interconnects by depositing a thin layer of a first conductive material on a wafer through a non-ionized deposition process. The thin layer overlays the wafer and lines any apertures in the wafer. Deposition of a first conductive material is followed by depositing another thin layer of a second conductive material by an ionized deposition process. In this manner, the second conductive material overlays the first conductive material and additionally lines the wafer and any apertures in the wafer. Furthermore, if the apertures open to underlying areas, the conductive materials that line the apertures preferably create a conductive film that can form a plurality of contacts between the conductive film and the underlying areas.
摘要翻译：通过非电离沉积工艺在晶片上沉积第一导电材料的薄层来提供一种方法来优选地产生坚固的触点和互连。薄层覆盖晶片并且对晶片中的任何孔进行排列。第一导电材料的沉积之后是通过电离沉积工艺沉积另一薄层的第二导电材料。以这种方式，第二导电材料覆盖第一导电材料，并且另外导引晶片和晶片中的任何孔。此外，如果孔向下面的区域打开，则线孔的导电材料优选地形成导电膜，该导电膜可以在导电膜和下面的区域之间形成多个接触。

6. 发明授权

US08604618B2 Structure and method for reducing vertical crack propagation 有权
标题翻译：减少垂直裂纹扩展的结构和方法
公开(公告)号：US08604618B2
公开(公告)日：2013-12-10
申请号：US13239533
申请日：2011-09-22
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Xiao Hu Liu , Thomas L. McDevitt , Gary L. Milo , William J. Murphy
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Xiao Hu Liu , Thomas L. McDevitt , Gary L. Milo , William J. Murphy
IPC分类号： H01L23/485 , H01L21/3205
CPC分类号： H01L21/76802 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.
摘要翻译：半导体器件及其制造方法包括在绝缘体上的垂直堆叠的层。每个层包括第一介电绝缘体部分，嵌入在第一介电绝缘体部分内的第一金属导体，覆盖第一金属导体的第一氮化物帽，第二电介质绝缘体部分，嵌入在第二介电绝缘体部分内的第二金属导体以及覆盖所述第二金属导体的第二氮化物帽。第一和第二金属导体形成第一垂直堆叠的导体层和第二垂直堆叠的导体层。第一垂直堆叠的导体层靠近第二垂直堆叠的导体层，并且至少一个气隙位于第一垂直堆叠的导体层和第二垂直堆叠的导体层之间。上半导体层覆盖第一垂直堆叠的导体层，气隙和第二多个垂直堆叠的导体层。

7. 发明申请

US20130075913A1 STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION 有权
公开(公告)号：US20130075913A1
公开(公告)日：2013-03-28
申请号：US13239533
申请日：2011-09-22
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Xiao Hu Liu , Thomas L. McDevitt , Gary L. Milo , William J. Murphy
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Xiao Hu Liu , Thomas L. McDevitt , Gary L. Milo , William J. Murphy
IPC分类号： H01L23/485 , H01L21/3205
CPC分类号： H01L21/76802 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

8. 发明申请

US20090212434A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR STRUCTURE 有权
标题翻译：制造半导体器件和半导体结构的方法
公开(公告)号：US20090212434A1
公开(公告)日：2009-08-27
申请号：US12035449
申请日：2008-02-22
申请人： Felix P. Anderson , Steven P. Barkyoumb , Edward C. Cooney, III , Thomas L. McDevitt , William J. Murphy , David C. Strippe
发明人： Felix P. Anderson , Steven P. Barkyoumb , Edward C. Cooney, III , Thomas L. McDevitt , William J. Murphy , David C. Strippe
IPC分类号： H01L21/768 , H01L23/538
CPC分类号： H01L23/53209 , C23C14/02 , C23C14/0641 , H01L21/2855 , H01L21/76843 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.
摘要翻译：提供了用于提高膜对半导体晶片和半导体结构的附着力的方法。通过实施本发明的方法，可以在晶片制造工艺期间显着抑制缺陷产生，例如减少颗粒产生。更具体地，所描述的工艺通过有效地增加TaN膜在晶片上的粘合性能，显着地减少了晶片的边缘或边缘（斜面）对TaN膜的剥落。在阻挡层制造过程中，相对于总钽加氮化物将氮化物的摩尔百分数提高到25％或更大的方法。

9. 发明授权

US07235487B2 Metal seed layer deposition 失效
标题翻译：金属种子层沉积
公开(公告)号：US07235487B2
公开(公告)日：2007-06-26
申请号：US10709562
申请日：2004-05-13
申请人： Steven P Barkyoumb , Jonathan D. Chapple-Sokol , Edward C. Cooney, III , Keith E. Downes , Thomas L. McDevitt , William J. Murphy
发明人： Steven P Barkyoumb , Jonathan D. Chapple-Sokol , Edward C. Cooney, III , Keith E. Downes , Thomas L. McDevitt , William J. Murphy
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76856 , H01L21/76859 , H01L21/76861 , H01L21/76862 , H01L21/76871 , H01L21/76873
摘要： A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.
摘要翻译：一种用于在半导体结构的制造过程中减少铜籽晶层的腐蚀的方法和结构。在结构（或包含结构的晶片）离开溅射工具的真空环境之前，将结构加热到高于溅射工具外部环境的水冷凝温度的温度。结果，当结构离开溅射工具时，水蒸气不会在结构上冷凝，因此防止了水蒸气对种子层的腐蚀。或者，在结构离开溅射工具环境之前，可以在籽晶层的顶部形成耐水蒸汽的保护层。在另一替代实施例中，种子层可以包括铜合金（例如用铝），其在暴露于水蒸汽时生长出耐水蒸气的保护层。

10. 发明授权

US08921144B2 Planar cavity MEMS and related structures, methods of manufacture and design structures 有权
标题翻译：平面腔MEMS及相关结构，制造方法和设计结构
公开(公告)号：US08921144B2
公开(公告)日：2014-12-30
申请号：US12973333
申请日：2010-12-20
申请人： George A. Dunbar, III , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper
发明人： George A. Dunbar, III , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper
IPC分类号： H01L21/00 , G06F17/50 , B81B3/00 , B81C1/00 , H01H57/00
CPC分类号： B81B3/0072 , B81B3/0021 , B81B2201/01 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81C1/0015 , B81C1/00365 , B81C1/00476 , B81C1/00619 , B81C1/00626 , B81C1/00666 , B81C2201/0109 , B81C2201/013 , B81C2201/0167 , B81C2201/017 , B81C2203/0136 , B81C2203/0172 , G06F17/5068 , G06F17/5072 , H01H1/0036 , H01H57/00 , H01H59/0009 , H01H2057/006 , H01L41/1136 , H01L2924/0002 , Y10S438/937 , Y10T29/42 , Y10T29/435 , Y10T29/49002 , Y10T29/49105 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/5313 , H01L2924/00
摘要： A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower sacrificial material used to form a lower cavity. The method further includes forming a cavity via connecting the lower cavity to an upper cavity. The cavity via is formed with a top view profile of rounded or chamfered edges. The method further includes forming an upper sacrificial material within and above the cavity via, which has a resultant surface based on the profile of the cavity via. The upper cavity is formed with a lid that is devoid of structures that would interfere with a MEMS beam, including: depositing a lid material on the resultant surface of the upper sacrificial material; and venting the upper sacrificial material to form the upper cavity such the lid material forms the lid which conforms with the resultant surface of the upper sacrificial material.
摘要翻译：形成至少一个微机电系统（MEMS）的方法包括形成用于形成下腔的较低牺牲材料。该方法还包括通过将下腔体连接到上部空腔来形成空腔。空腔通孔形成有圆形或倒角边缘的顶视图。该方法还包括在空腔内部和上方形成上部牺牲材料，其具有基于空腔通路的轮廓的合成表面。上空腔形成有没有会干扰MEMS梁的结构的盖，包括：在上牺牲材料的所得表面上沉积盖材料; 并且排出上部牺牲材料以形成上部空腔，使得盖子材料形成与上部牺牲材料的合成表面一致的盖子。

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