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1. 发明申请

US20050212063A1 Thin-film transistor formed on insulating substrate 失效
标题翻译：绝缘基板上形成薄膜晶体管
公开(公告)号：US20050212063A1
公开(公告)日：2005-09-29
申请号：US11085111
申请日：2005-03-22
申请人： Fumiki Nakano , Genshiro Kawachi , Yoshiaki Nakazaki , Shinzo Tsuboi , Takahiko Endo , Tomoya Kato
发明人： Fumiki Nakano , Genshiro Kawachi , Yoshiaki Nakazaki , Shinzo Tsuboi , Takahiko Endo , Tomoya Kato
IPC分类号： H01L21/336 , H01L21/77 , H01L21/8236 , H01L21/84 , H01L27/12 , H01L29/04 , H01L29/786
CPC分类号： H01L27/1296 , H01L27/1285 , H01L29/04 , H01L29/66757 , H01L29/78696
摘要： There is provided a thin-film transistor that is formed on an insulating substrate, is capable of a high-speed operation, has small non-uniformity among devices, is hardly susceptible to device destruction due to high voltage, and is free from the effect of a parasitic transistor that forms at an edge part of an Si island. The thin-film semiconductor device is formed using a thin-film semiconductor provided on the insulating substrate and includes a gate region for formation of a channel region through which a drain current flows. The gate region has a ring shape in plan on the insulating substrate. High concentration impurity-doped regions are dividedly provided on an inside and an outside of the ring-shaped gate region, and the channel region is formed of a plurality of fan-shaped semiconductor single-crystal portions.
摘要翻译：提供一种薄膜晶体管，其形成在绝缘基板上，能够进行高速运转，器件之间的不均匀性较小，几乎不易受高电压造成的器件破坏，并且不受影响形成在Si岛的边缘部分的寄生晶体管。薄膜半导体器件使用设置在绝缘基板上的薄膜半导体形成，并且包括用于形成漏极电流流过的沟道区域的栅极区域。栅极区域在绝缘基板上具有平面的环形形状。高浓度杂质掺杂区被分割地设置在环形栅极区域的内部和外部，并且沟道区域由多个扇形半导体单晶部分形成。

2. 发明授权

US07309900B2 Thin-film transistor formed on insulating substrate 失效
标题翻译：绝缘基板上形成薄膜晶体管
公开(公告)号：US07309900B2
公开(公告)日：2007-12-18
申请号：US11085111
申请日：2005-03-22
申请人： Fumiki Nakano , Genshiro Kawachi , Yoshiaki Nakazaki , Shinzo Tsuboi , Takahiko Endo , Tomoya Kato
发明人： Fumiki Nakano , Genshiro Kawachi , Yoshiaki Nakazaki , Shinzo Tsuboi , Takahiko Endo , Tomoya Kato
IPC分类号： H01L29/76
CPC分类号： H01L27/1296 , H01L27/1285 , H01L29/04 , H01L29/66757 , H01L29/78696
摘要： There is provided a thin-film transistor that is formed on an insulating substrate, is capable of a high-speed operation, has small non-uniformity among devices, is hardly susceptible to device destruction due to high voltage, and is free from the effect of a parasitic transistor that forms at an edge part of an Si island. The thin-film semiconductor device is formed using a thin-film semiconductor provided on the insulating substrate and includes a gate region for formation of a channel region through which a drain current flows. The gate region has a ring shape in plan on the insulating substrate. High concentration impurity-doped regions are dividedly provided on an inside and an outside of the ring-shaped gate region, and the channel region is formed of a plurality of fan-shaped semiconductor single-crystal portions.
摘要翻译：提供一种薄膜晶体管，其形成在绝缘基板上，能够进行高速运转，器件之间的不均匀性较小，几乎不易受高电压造成的器件破坏，并且不受影响形成在Si岛的边缘部分的寄生晶体管。薄膜半导体器件使用设置在绝缘基板上的薄膜半导体形成，并且包括用于形成漏极电流流过的沟道区域的栅极区域。栅极区域在绝缘基板上具有平面的环形形状。高浓度杂质掺杂区被分割地设置在环形栅极区域的内部和外部，并且沟道区域由多个扇形半导体单晶部分形成。

3. 发明申请

US20070228469A1 THIN-FILM TRANSISTOR FORMED ON INSULATING SUBSTRATE 审中-公开
标题翻译：形成绝缘基板的薄膜晶体管
公开(公告)号：US20070228469A1
公开(公告)日：2007-10-04
申请号：US11758217
申请日：2007-06-05
申请人： Fumiki Nakano , Genshiro Kawachi , Yoshiaki Nakazaki , Shinzo Tsuboi , Takahiko Endo , Tomoya Kato
发明人： Fumiki Nakano , Genshiro Kawachi , Yoshiaki Nakazaki , Shinzo Tsuboi , Takahiko Endo , Tomoya Kato
IPC分类号： H01L29/786 , H01L27/12
CPC分类号： H01L27/1296 , H01L27/1285 , H01L29/04 , H01L29/66757 , H01L29/78696
摘要： There is provided a thin-film transistor that is formed on an insulating substrate, is capable of a high-speed operation, has small non-uniformity among devices, is hardly susceptible to device destruction due to high voltage, and is free from the effect of a parasitic transistor that forms at an edge part of an Si island. The thin-film semiconductor device is formed using a thin-film semiconductor provided on the insulating substrate and includes a gate region for formation of a channel region through which a drain current flows. The gate region has a ring shape in plan on the insulating substrate. High concentration impurity-doped regions are dividedly provided on an inside and an outside of the ring-shaped gate region, and the channel region is formed of a plurality of fan-shaped semiconductor single-crystal portions.
摘要翻译：提供一种薄膜晶体管，其形成在绝缘基板上，能够进行高速运转，器件之间的不均匀性较小，几乎不易受高电压造成的器件破坏，并且不受影响形成在Si岛的边缘部分的寄生晶体管。薄膜半导体器件使用设置在绝缘基板上的薄膜半导体形成，并且包括用于形成漏极电流流过的沟道区域的栅极区域。栅极区域在绝缘基板上具有平面的环形形状。高浓度杂质掺杂区被分割地设置在环形栅极区域的内部和外部，并且沟道区域由多个扇形半导体单晶部分形成。

4. 发明申请

US20060033104A1 Thin film transistor, method of manufacturing thin film transistor, and display device 审中-公开
标题翻译：薄膜晶体管，制造薄膜晶体管的方法和显示装置
公开(公告)号：US20060033104A1
公开(公告)日：2006-02-16
申请号：US11197637
申请日：2005-08-05
申请人： Yoshiaki Nakazaki , Fumiki Nakano , Genshiro Kawachi , Terunori Warabisako , Masayuki Jyumonji , Hiroyuki Ogawa , Masato Hiramatsu , Tomoya Kato
发明人： Yoshiaki Nakazaki , Fumiki Nakano , Genshiro Kawachi , Terunori Warabisako , Masayuki Jyumonji , Hiroyuki Ogawa , Masato Hiramatsu , Tomoya Kato
IPC分类号： H01L29/04 , H01L29/76 , H01L27/12
CPC分类号： H01L21/02675 , B23K26/073 , G02F1/13454 , H01L21/2026 , H01L27/1296 , H01L29/04 , H01L29/66757 , H01L29/78618 , H01L29/78675 , H01L29/78696
摘要： There is disclosed a thin film transistor having a source region, a channel region, and a drain region in a semiconductor thin film whose crystals have grown in a transverse direction, the thin film transistor having a gate insulating film and a gate electrode in an upper part of the channel region, wherein a channel-region-side edge portion of the drain region or the source region is disposed in such a manner as to be positioned in the vicinity of an end position of lateral growth.
摘要翻译：公开了一种在半导体薄膜中具有晶体沿横向生长的源极区，沟道区和漏极区的薄膜晶体管，薄膜晶体管具有栅极绝缘膜和位于上部的栅电极沟道区域的一部分，其中漏极区域或源极区域的沟道区域侧边缘部分以这样的方式设置，以便位于横向生长的结束位置附近。

5. 发明授权

US08654291B2 Pixel circuit and display device 有权
标题翻译：像素电路和显示设备
公开(公告)号：US08654291B2
公开(公告)日：2014-02-18
申请号：US13504074
申请日：2010-10-21
申请人： Naoki Ueda , Yoshimitsu Yamauchi , Fumiki Nakano
发明人： Naoki Ueda , Yoshimitsu Yamauchi , Fumiki Nakano
IPC分类号： G02F1/1337
CPC分类号： G09G3/367 , G02F1/13624 , G09G3/3618 , G09G3/3655 , G09G3/3659 , G09G2300/0814 , G09G2300/0876
摘要： A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.
摘要翻译：提供了一种在不降低开口率的情况下实现低功耗的显示装置。液晶电容元件Clc被夹在像素电极20和相对电极80之间。像素电极20，第一开关电路22的一端，第二开关电路23的一端和第二晶体管T2的第一端形成内部节点N1。第一开关电路22和第二开关电路23的其他端子连接到源极线SL。第二开关电路23是由第一晶体管T1和二极管D1组成的串联电路。第一晶体管T1的控制端子，第二晶体管T2的第二端子和升压电容元件Cbst的一端形成输出节点N2。升压电容元件Cbst的另一端和第二晶体管T2的控制端分别连接到升压线BST和基准线REF。二极管D1具有从源极线SL到内部节点N1的整流功能。

6. 发明授权

US08310638B2 Pixel circuit and display apparatus 有权
标题翻译：像素电路和显示设备
公开(公告)号：US08310638B2
公开(公告)日：2012-11-13
申请号：US13504609
申请日：2010-07-22
申请人： Yoshimitsu Yamauchi , Naoki Ueda , Fumiki Nakano
发明人： Yoshimitsu Yamauchi , Naoki Ueda , Fumiki Nakano
IPC分类号： G02F1/1337
CPC分类号： G09G3/3659 , G02F1/13624 , G09G2300/0465 , G09G2300/0876 , G09G2300/089 , G09G2310/08 , G09G2330/021
摘要： Disclosed is a display device that can achieve a reduction of power consumption without deteriorating the aperture ratio. A liquid crystal capacitance element (Clc) is formed by being sandwiched between a pixel electrode (20) and an opposite electrode (80). The pixel electrode (20), one end of a first switching circuit (22), one end of a second switching circuit (23), and the first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switching circuit (22) and the other end of the second switching circuit (23) are connected to a source line (SL). The second switching circuit (23) includes a series circuit of a transistor (T1) and a diode (D1), and an output node (N2) is formed of the control terminal of the transistor (T1), the second terminal of the transistor (T2), and one end of a boost capacitance element (Cbst). The other end of the boost capacitance element (Cbst) is connected to a boost line (BST), and the control terminal of the transistor (T2) is connected to a reference line (REF). The diode (D1) has a rectifying function in the direction to the internal node (N1) from the source line (SL).
摘要翻译：公开了一种能够在不损害开口率的情况下实现功耗的降低的显示装置。通过夹在像素电极（20）和相对电极（80）之间形成液晶电容元件（Clc）。像素电极（20），第一开关电路（22）的一端，第二开关电路（23）的一端和第二晶体管（T2）的第一端子形成内部节点（N1）。第一开关电路（22）的另一端和第二开关电路（23）的另一端连接到源极线（SL）。第二开关电路（23）包括晶体管（T1）和二极管（D1）的串联电路，输出节点（N2）由晶体管（T1）的控制端子形成，晶体管的第二端子（T2）和升压电容元件（Cbst）的一端。升压电容元件（Cbst）的另一端连接到升压线（BST），晶体管（T2）的控制端子连接到基准线（REF）。二极管（D1）在从源极线（SL）到内部节点（N1）的方向上具有整流功能。

7. 发明申请

US20050272274A1 Apparatus for forming a semiconductor thin film 有权
标题翻译：用于形成半导体薄膜的装置
公开(公告)号：US20050272274A1
公开(公告)日：2005-12-08
申请号：US11198656
申请日：2005-08-05
申请人： Masakiyo Matsumura , Mikihiko Nishitani , Yoshinobu Kimura , Masayuki Jyumonji , Yukio Taniguchi , Masato Hiramatsu , Fumiki Nakano
发明人： Masakiyo Matsumura , Mikihiko Nishitani , Yoshinobu Kimura , Masayuki Jyumonji , Yukio Taniguchi , Masato Hiramatsu , Fumiki Nakano
IPC分类号： B23K26/06 , C30B1/00 , C30B13/00 , C30B13/24 , H01L21/20 , H01L21/268 , H01L21/26
CPC分类号： H01L21/02678 , B23K26/06 , B23K26/066 , B23K2101/40 , C30B1/00 , C30B13/24 , C30B29/06 , H01L21/02691 , H01L21/2026 , Y10T117/1004 , Y10T117/1008 , Y10T117/1016
摘要： Disclosed are apparatus for forming a semiconductor film having an excellent crystallinity from a non-single crystal semiconducting layer formed on a base layer made of an insulating material. The apparatus includes a light source, a homogenizer for homogenizing an intensity distribution of the emitted light, an amplitude-modulation means for performing the amplitude-modulation such that the amplitude of the light, of which the intensity distribution is homogenized, is increased in the direction of the relative motion of the light to the base layer, an optional light projection optical system for projecting the amplitude-modulated light onto the surface of the non-single crystal semiconductor such that a predetermined irradiation energy can be obtained, a phase shifter for providing a low temperature point in the surface irradiated by the light, and a substrate stage to move the light relative to the substrate thereby enabling scanning in the X and Y axis.
摘要翻译：公开了一种从由绝缘材料制成的基底层上形成的非单晶半导体层形成具有优异结晶度的半导体膜的装置。该装置包括光源，用于均匀化发射光的强度分布的均质器，用于执行调幅的幅度调制装置，使得强度分布均匀化的光的振幅在光向基层的相对运动的方向，用于将调幅光投影到非单晶半导体的表面上以使得能够获得预定的照射能量的可选的光投射光学系统，用于在由光照射的表面中提供低温点，以及衬底台，以相对于衬底移动光，从而使得能够在X和Y轴上进行扫描。

8. 发明申请

US20120218246A1 PIXEL CIRCUIT AND DISPLAY DEVICE 有权
标题翻译：像素电路和显示设备
公开(公告)号：US20120218246A1
公开(公告)日：2012-08-30
申请号：US13504074
申请日：2010-10-21
申请人： Naoki Ueda , Yoshimitsu Yamauchi , Fumiki Nakano
发明人： Naoki Ueda , Yoshimitsu Yamauchi , Fumiki Nakano
IPC分类号： G09G5/00
CPC分类号： G09G3/367 , G02F1/13624 , G09G3/3618 , G09G3/3655 , G09G3/3659 , G09G2300/0814 , G09G2300/0876
摘要： A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.
摘要翻译：提供了一种在不降低开口率的情况下实现低功耗的显示装置。液晶电容元件Clc被夹在像素电极20和相对电极80之间。像素电极20，第一开关电路22的一端，第二开关电路23的一端和第二晶体管T2的第一端形成内部节点N1。第一开关电路22和第二开关电路23的其他端子连接到源极线SL。第二开关电路23是由第一晶体管T1和二极管D1组成的串联电路。第一晶体管T1的控制端子，第二晶体管T2的第二端子和升压电容元件Cbst的一端形成输出节点N2。升压电容元件Cbst的另一端和第二晶体管T2的控制端分别连接到升压线BST和基准线REF。二极管D1具有从源极线SL到内部节点N1的整流功能。

9. 发明授权

US06946367B2 Methods for forming a semiconductor thin film 有权
标题翻译：形成半导体薄膜的方法
公开(公告)号：US06946367B2
公开(公告)日：2005-09-20
申请号：US10366754
申请日：2003-02-13
申请人： Masakiyo Matsumura , Mikihiko Nishitani , Yoshinobu Kimura , Masayuki Jyumonji , Yukio Taniguchi , Masato Hiramatsu , Fumiki Nakano
发明人： Masakiyo Matsumura , Mikihiko Nishitani , Yoshinobu Kimura , Masayuki Jyumonji , Yukio Taniguchi , Masato Hiramatsu , Fumiki Nakano
IPC分类号： B23K26/06 , C30B1/00 , C30B13/00 , C30B13/24 , H01L21/20 , H01L21/268 , H01L21/322
CPC分类号： H01L21/02678 , B23K26/06 , B23K26/066 , B23K2101/40 , C30B1/00 , C30B13/24 , C30B29/06 , H01L21/02691 , H01L21/2026 , Y10T117/1004 , Y10T117/1008 , Y10T117/1016
摘要： Methods for forming a single crystal semiconductor thin film layer from a non-single crystal layer includes directing a light source having a homogenized intensity distribution and a modulated amplitude towards the non-single crystal layer, and relatively moving the light with respect to the layer wherein the amplitude of the conditioned light is preferably increased in the direction of relative motion of the light to the layer. Preferred methods also include multiple light exposures in overlapping series to form ribbon-shaped single crystal regions, and providing a low temperature point in the semiconductor layer to generate a starting location for single crystalization.
摘要翻译：从非单晶层形成单晶半导体薄膜层的方法包括将具有均匀强度分布和调制振幅的光源引向非单晶层，并相对于其相对移动光，调节后的光的振幅优选在光的相对运动方向上增加。优选的方法还包括重叠系列中的多次曝光以形成带状单晶区域，并且在半导体层中提供低温点以产生用于单晶化的起始位置。

10. 发明授权

US08942460B2 Medical image processing apparatus that normalizes a distance between an inner wall and outer wall of the myocardial region 有权
标题翻译：使心肌区域的内壁和外壁之间的距离归一化的医用图像处理装置
公开(公告)号：US08942460B2
公开(公告)日：2015-01-27
申请号：US13523132
申请日：2012-06-14
申请人： Fumiki Nakano , Tomohiro Kawasaki
发明人： Fumiki Nakano , Tomohiro Kawasaki
IPC分类号： G06K9/00 , G06T11/20 , A61B6/03 , A61B6/00 , A61B8/08
CPC分类号： G06T11/206 , A61B6/032 , A61B6/037 , A61B6/503 , A61B6/5217 , A61B6/5235 , A61B6/5247 , A61B8/0883 , A61B8/483 , A61B8/5261
摘要： According to one embodiment, storage unit stores three-dimensional function image data concerning a function index of the heart. The extraction unit extracts a myocardial region from the three-dimensional function image data. The normalization unit normalizes the distance between the inner wall and outer wall of the myocardial region with a predetermined numerical value range. The generation unit generates a bull's eye map expressing a spatial distribution of pixel values at positions on the myocardial region by two-dimensional polar coordinates. The positions correspond to predetermined values in the predetermined numerical value range. The display unit displays the bull's eye map.
摘要翻译：根据一个实施例，存储单元存储关于心脏的功能索引的三维功能图像数据。提取单元从三维功能图像数据提取心肌区域。标准化单元以预定的数值范围归一化心肌区域的内壁和外壁之间的距离。生成单元通过二维极坐标生成表示心肌区域上的位置的像素值的空间分布的公牛眼图。位置对应于预定数值范围内的预定值。显示单元显示公牛的眼图。

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