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1. 发明授权

US10447389B2 Managing data flow in VCSEL-based optical communications system 有权
公开(公告)号：US10447389B2
公开(公告)日：2019-10-15
申请号：US15686304
申请日：2017-08-25
申请人： GLOBALFOUNDRIES Inc. , International Business Machines Corporation
发明人： Hayden C. Cranford, Jr. , Jonathan E. Proesel , Rashmi R. Bindu
IPC分类号： H04B10/079 , H04B10/50 , H01S5/068
摘要： Methods according to the disclosure include methods for managing data flow in an optical communications system having a plurality of vertical cavity surface emitting lasers (VCSELs). The method generally includes determining whether operation of the system exceeds a thermal threshold for a thermal parameter of the system, and switching from a first data bandwidth to a second data bandwidth when the thermal threshold is exceeded. Operation at the second data bandwidth further includes determining whether further operation of the system demands the first data bandwidth, and resuming operation of the system at the first data bandwidth only when the thermal parameter during operation at the second data bandwidth does not exceed the thermal threshold.

2. 发明授权

US10250010B1 Control of VCSEL-based optical communications system 有权
公开(公告)号：US10250010B1
公开(公告)日：2019-04-02
申请号：US15982459
申请日：2018-05-17
申请人： GLOBALFOUNDRIES INC. , International Business Machines Corporation
发明人： Hayden C. Cranford, Jr. , Rashmi R. Bindu , Jonathan E. Proesel
IPC分类号： H04B10/04 , H01S5/026 , H01S5/183 , H04B10/69 , H04B10/564 , H04B10/50 , H01S5/0683
摘要： Methods according to the disclosure include methods for controlling an optical communications system. The method may include adjusting a VCSEL transmitter of the optical communications system to operate at a second data bandwidth distinct from its first data bandwidth; reducing a data flow rate of a receiver during operation of the optical communications system at the second data bandwidth; determining whether a system quality metric for the receiver meets a specification requirement; in response to determining the system quality metric does not meet the specification requirement, adjusting an operational setting of the VCSEL transmitter or the receiver; in response to determining the system quality metric meets the specification requirement, continuing operation of the optical communications system at the second data bandwidth; and in response to receiving an override signal, resuming operation of the optical communications system at the first data bandwidth.

3. 发明授权

US09209948B2 Testing a decision feedback equalizer (‘DFE’) 有权
标题翻译：测试反馈均衡器（'DFE'）
公开(公告)号：US09209948B2
公开(公告)日：2015-12-08
申请号：US14599605
申请日：2015-01-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eugene R. Atwood , Matthew B. Baecher , Minhan Chen , Hayden C. Cranford, Jr. , William R. Kelly , Todd M. Rasmus
IPC分类号： H04B17/00 , H04L1/24 , H04L25/03 , H04B17/20
CPC分类号： H04L1/244 , H04B17/00 , H04B17/20 , H04L25/03057 , H04L25/03248
摘要： Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
摘要翻译：测试判决反馈均衡器（DFE），DFE包括可操作地耦合到多个锁存器的加法放大器和用于接收数据信号的输入信号线，包括：防止差分数据信号被加法放大器接收; 并对每个要测试的水龙头进行迭代：将每个水龙头的抽头系数设置为零; 将所述多个锁存器的输出设置为预定值; 将要测试的水龙头的抽头系数设置为满量程值; 以及确定来自所述DFE的合成输出信号是否与预定的预期输出信号匹配。

4. 发明授权

US09231796B2 Power aware equalization in a serial communications link 有权
标题翻译：串行通信链路中的功率感知均衡
公开(公告)号：US09231796B2
公开(公告)日：2016-01-05
申请号：US14088484
申请日：2013-11-25
申请人： International Business Machines Corporation
发明人： John F. Bulzacchelli , Hayden C. Cranford, Jr. , Daniel M. Dreps , David W. Siljenberg
IPC分类号： H04L25/03
CPC分类号： H04L25/03885 , H04L25/03006 , H04L25/03114 , H04L25/03159 , H04L2025/03566 , H04L2025/03592
摘要： Power aware equalization in a serial communications link that includes a transmitter and a receiver, including: determining, by a power aware equalization module, a required signal eye width and a required signal eye height for signals received by the receiver; identifying one or more signal equalizers for signals transmitted over the serial communications link; identifying one or more cumulative equalizer settings that equalize signals transmitted over the serial communications link to conform with the required signal eye width and the required signal eye height for signals received by the receiver; determining power consumption values associated with each of the one or more cumulative equalizer settings; and setting the one or more signal equalizers to configuration settings in dependence upon the power consumption values associated with each of the one or more cumulative equalizer settings.
摘要翻译：包括发射机和接收机的串行通信链路中的功率感知均衡包括：由功率感知均衡模块确定由接收机接收的信号所需的信号眼睛宽度和所需信号眼睛高度; 识别通过串行通信链路传输的信号的一个或多个信号均衡器; 识别均衡通过串行通信链路发送的信号的一个或多个累积均衡器设置，以符合由接收机接收的信号的所需信号眼宽度和所需信号眼睛高度; 确定与所述一个或多个累积均衡器设置中的每一个相关联的功耗值; 以及根据与所述一个或多个累积均衡器设置中的每一个相关联的功耗值，将所述一个或多个信号均衡器设置为配置设置。

5. 发明授权

US09014254B2 Testing a decision feedback equalizer (‘DFE’) 有权
公开(公告)号：US09014254B2
公开(公告)日：2015-04-21
申请号：US13921470
申请日：2013-06-19
申请人： International Business Machines Corporation
发明人： Eugene R. Atwood , Matthew B. Baecher , Minhan Chen , Hayden C. Cranford, Jr. , William R. Kelly , Todd M. Rasmus
IPC分类号： H03K5/159 , H04B17/00
CPC分类号： H04L1/244 , H04B17/00 , H04B17/20 , H04L25/03057 , H04L25/03248
摘要： Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

6. 发明授权

US08653597B2 Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip 有权
标题翻译：用于在非常薄的绝缘体上（ETSOI）集成电路芯片上控制体偏置的解决方案
公开(公告)号：US08653597B2
公开(公告)日：2014-02-18
申请号：US13739222
申请日：2013-01-11
申请人： International Business Machines Corporation
发明人： Hayden C. Cranford, Jr. , Terence B. Hook
IPC分类号： H01L27/12
CPC分类号： G05F1/10 , H01L27/092 , H01L27/1203
摘要： Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.
摘要翻译：公开了用于优化跨越ETSOI设备的衬底的体偏压的解决方案。在一个实施例中，公开了一种用于优化跨越ETSOI设备的衬底的体偏压的装置，包括：用于感测至少一个预定电路参数的感测电路; 用于向ETSOI装置的基板施加偏置电压的充电电路; 以及连接到所述感测电路和所述充电电路的处理电路，所述处理电路被配置为接收所述感测电路的输出，并且响应于确定所述偏置电压是否偏离于所述偏置电压而调整施加到所述ETSOI器件的衬底的偏置电压目标金额。

7. 发明授权

US08989313B2 Adaptable receiver detection 有权
标题翻译：适应接收机检测
公开(公告)号：US08989313B2
公开(公告)日：2015-03-24
申请号：US13792281
申请日：2013-03-11
申请人： International Business Machines Corporation
发明人： John J. Bergkvist, Jr. , Steven M. Clements , Carrie E. Cox , Hayden C. Cranford, Jr. , Todd E. Leonard
IPC分类号： H04B17/00
CPC分类号： H04B17/0037 , H04B17/104
摘要： Methods and apparatuses for adaptable receiver detection are provided. Embodiments include providing, by receiver detection circuitry at a transmitter coupled to a communication link, a voltage to the communication link; determining, by the receiver detection circuitry, a rise time corresponding to a rising edge change of the voltage on the communication link; determining, by the receiver detection circuitry, a fall time corresponding to a falling edge change of the voltage on the communication link; and determining, by the receiver detection circuitry, whether the rise time and the fall time are consistent with the transmitter being coupled through the communication link to a remote receiver.
摘要翻译：提供了适应性接收机检测的方法和装置。实施例包括通过耦合到通信链路的发射机的接收机检测电路向通信链路提供电压; 由所述接收机检测电路确定与所述通信链路上的电压的上升沿变化相对应的上升时间; 由所述接收机检测电路确定对应于所述通信链路上的电压的下降沿变化的下降时间; 以及由接收机检测电路确定上升时间和下降时间是否与通过通信链路耦合到远程接收机的发射机一致。

8. 发明申请

US20130120055A1 SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIP 有权
公开(公告)号：US20130120055A1
公开(公告)日：2013-05-16
申请号：US13739222
申请日：2013-01-11
申请人： International Business Machines Corporation
发明人： Hayden C. Cranford, Jr. , Terence B. Hook
IPC分类号： G05F1/10 , H01L27/092
CPC分类号： G05F1/10 , H01L27/092 , H01L27/1203
摘要： Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

9. 发明授权

US09853612B1 Peaking amplifier frequency tuning 有权
公开(公告)号：US09853612B1
公开(公告)日：2017-12-26
申请号：US15467589
申请日：2017-03-23
申请人： GLOBALFOUNDRIES Inc.
发明人： Michael Chen , Steven M. Clements , Mohak Chhabra , Steven E. Mikes , Hayden C. Cranford, Jr.
IPC分类号： H03F1/48 , H03F3/191 , H03F3/68
CPC分类号： H03F1/486 , H03F1/34 , H03F3/195 , H03F3/211 , H03F2200/135
摘要： A circuit including: input and output nodes and first and second feedback nodes; a first input amplifier having an input connected to the input node and an output connected to the first feedback node; a second input amplifier having an input connected to the input node and an output connected to the second feedback node; a capacitor connecting the first feedback node and the second feedback node; an amplifier having an input connected to the first feedback node and an output connected to the output node; a base feedback amplifier with an input connected to the output node and an output connected to the first feedback node; a tunable feedback amplifier with an input connected to the output node and an output connected to the second feedback node; and a tuning circuit for varying a transconductance of the tunable feedback circuit and operational frequency of the peaking amplifier circuit.

10. 发明授权

US10432209B1 Linear feedback shift register-based clock signal generator, time domain-interleaved analog to digital converter and methods 有权
公开(公告)号：US10432209B1
公开(公告)日：2019-10-01
申请号：US16156460
申请日：2018-10-10
申请人： GLOBALFOUNDRIES INC.
发明人： Steven E. Mikes , Hayden C. Cranford, Jr. , John K. Koehler , Steven J. Baumgartner
IPC分类号： H03M1/10 , H03M1/12 , H03K23/54
摘要： Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK0). Based on the multi-bit states, a single-phase pulse generator generates first and second clock signals (CLK1 and CLK2), where the pulse rate of CLK1 is slower than that of the CLK0 and greater than that of CLK2. In some embodiments, a first multi-phase pulse generator can generate N-phases of the CLK1 based on CLK1 and N-phases of the CLK0 and a second multi-phase pulse generator can generate N-phases of CLK2 based on CLK2 and N-phases of CLK0. Furthermore, additional registers can optionally use the N-phases of CLK2 to further generate N sets of M-phases of the CLK2. Also disclosed are a multi-level circuit (e.g., a time domain-interleaved analog-to-digital converter (ADC)), which incorporates the LFSR-based clock signal generator, and associated methods.

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