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    • 1. 发明申请
    • Method for Replicating and Synchronizing a Plurality of Physical Instances with a Logical Master
    • 使用逻辑主机复制和同步多个物理实例的方法
    • US20080059952A1
    • 2008-03-06
    • US11468031
    • 2006-08-29
    • Gary A. Van HubenDavid A. WebberChristopher J. Berry
    • Gary A. Van HubenDavid A. WebberChristopher J. Berry
    • G06F9/44
    • G06F17/30575G06F11/2094
    • Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets. This permits all existing verification processes that are normally executed against the common data set to also be equally applied to the clones of said data set by way of automatic synchronization between of the common dataset and the clones.
    • 设计数据管理使用一个共同的数据集副本以及多个实例,同时继续利用现有的设计数据库和现有的CAD工具。 允许最小量的用户干预来创建和维护公共数据集,设计数据管理使用将一般数据集复制到一个或多个克隆数据集中。 该方法优选地提供用于复制和同步一个或多个数据集与主数据集,包括提供主数据集和至少一个克隆数据集的数据设计管理,以及将主物理设计数据集复制到一个或多个物理 允许定制所述一个或多个物理实例的实例。 主数据集描述了设计组件,电路宏和电路实体中的至少一个,并且包括逻辑数据集,并且它包括物理设计数据集。 这允许通常针对公共数据集执行的所有现有验证过程也可以通过公共数据集和克隆之间的自动同步同样地应用于所述数据集的克隆。
    • 2. 发明授权
    • Method for replicating and synchronizing a plurality of physical instances with a logical master
    • 用于使用逻辑主机复制和同步多个物理实例的方法
    • US07735051B2
    • 2010-06-08
    • US11468031
    • 2006-08-29
    • Gary A. Van HubenDavid A. WebberChristopher J. Berry
    • Gary A. Van HubenDavid A. WebberChristopher J. Berry
    • G06F17/50
    • G06F17/30575G06F11/2094
    • Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets. This permits all existing verification processes that are normally executed against the common data set to also be equally applied to the clones of said data set by way of automatic synchronization between of the common dataset and the clones.
    • 设计数据管理使用一个共同的数据集副本以及多个实例,同时继续利用现有的设计数据库和现有的CAD工具。 允许最小量的用户干预来创建和维护公共数据集,设计数据管理使用将一般数据集复制到一个或多个克隆数据集中。 该方法优选地提供用于复制和同步一个或多个数据集与主数据集,包括提供主数据集和至少一个克隆数据集的数据设计管理,以及将主物理设计数据集复制到一个或多个物理 允许定制所述一个或多个物理实例的实例。 主数据集描述了设计组件,电路宏和电路实体中的至少一个,并且包括逻辑数据集,并且它包括物理设计数据集。 这允许通常针对公共数据集执行的所有现有验证过程也可以通过公共数据集和克隆之间的自动同步同样地应用于所述数据集的克隆。
    • 3. 发明授权
    • Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements
    • 可编程总线驱动器启动延迟/周期延迟以减少弹性接口弹性要求
    • US07783911B2
    • 2010-08-24
    • US11426666
    • 2006-06-27
    • Jonathan Y. ChenPatrick J. MeaneyGary A. Van HubenDavid A. Webber
    • Jonathan Y. ChenPatrick J. MeaneyGary A. Van HubenDavid A. Webber
    • G06F11/00G06F13/42H04L7/00
    • G11C7/1051G11C7/1066G11C7/1069
    • A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency.
    • 双数据速率弹性界面,其中可编程锁定级提供弹性延迟,优选地在弹性界面的驱动侧。 然而,本发明不限于驱动器侧/芯片,也可以在接收机侧/芯片中实现。 然而,由于弹性接口的接收机侧已经具有复杂的逻辑,因此本发明通常在驱动侧实现。 接口驱动芯片侧的可编程锁存级通常可以以本地时钟频率(与弹性接口总线时钟频率相同的频率)工作,而这又是接收锁存级的双倍数据速率的一半 操作,从而减少接口接收机中的逻辑和存储资源。 在本地时钟频率是弹性接口总线时钟频率的两倍的情况下,也可以使用可编程锁存级。
    • 4. 发明申请
    • Programmable Bus Driver Launch Delay/Cycle Delay to Reduce Elastic Interface Elasticity Requirements
    • 可编程总线驱动器启动延迟/周期延迟以减少弹性接口弹性要求
    • US20070300099A1
    • 2007-12-27
    • US11426666
    • 2006-06-27
    • Jonathan Y. ChenPatrick J. MeaneyGary A. Van HubenDavid A. Webber
    • Jonathan Y. ChenPatrick J. MeaneyGary A. Van HubenDavid A. Webber
    • G06F1/00
    • G11C7/1051G11C7/1066G11C7/1069
    • A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency.
    • 双数据速率弹性界面,其中可编程锁定级提供弹性延迟,优选地在弹性界面的驱动侧。 然而,本发明不限于驱动器侧/芯片,也可以在接收机侧/芯片中实现。 然而,由于弹性接口的接收机侧已经具有复杂的逻辑,因此本发明通常在驱动侧实现。 接口驱动芯片侧的可编程锁存级通常可以以本地时钟频率(与弹性接口总线时钟频率相同的频率)工作,而这又是接收锁存级的双倍数据速率的一半 操作,从而减少接口接收机中的逻辑和存储资源。 在本地时钟频率是弹性接口总线时钟频率的两倍的情况下,也可以使用可编程锁存级。
    • 5. 发明授权
    • Mechanism for windaging of a double rate driver
    • 双速率驱动程序的机制
    • US07734944B2
    • 2010-06-08
    • US11426648
    • 2006-06-27
    • Jonathan Y. ChenJeffrey A. MageeDavid A. Webber
    • Jonathan Y. ChenJeffrey A. MageeDavid A. Webber
    • G06F5/06G06F13/42H04L7/00
    • G06F1/12
    • A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.
    • 双数据速率发射系统和方法,其中两对一多路复用器选择信号延迟是可编程的,并且可以针对每个系统单独调整。 这允许根据所需的实际设置时间而不是最坏的设置时间来最小化延迟量。 到复用器的选择信号被充分延迟以补偿多路复用器的输入处的数据的占空比的不均匀性。 不均匀性的补偿允许导线上的数据对于所有传输的数据具有统一的占空比,而不考虑哪个锁存器来源数据。 选择来自两个锁存器的数据的多路复用器,这些数据是在不同时钟边沿发射数据的,具有延迟一个可变量的选择线,以调整选择,使得数据在所有端口上的多路复用器的输入处是干净的。
    • 9. 发明申请
    • Mechanism for Windaging of a Double Rate Driver
    • 双速率驱动程序的机制
    • US20070300098A1
    • 2007-12-27
    • US11426648
    • 2006-06-27
    • Jonathan Y. ChenJeffrey A. MageeDavid A. Webber
    • Jonathan Y. ChenJeffrey A. MageeDavid A. Webber
    • G06F1/12
    • G06F1/12
    • A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.
    • 双数据速率发射系统和方法,其中两对一多路复用器选择信号延迟是可编程的,并且可以针对每个系统单独调整。 这允许根据所需的实际设置时间而不是最坏的设置时间来最小化延迟量。 到复用器的选择信号被充分延迟以补偿多路复用器的输入处的数据的占空比的不均匀性。 不均匀性的补偿允许导线上的数据对于所有传输的数据具有统一的占空比,而不考虑哪个锁存器来源数据。 选择来自两个锁存器的数据的多路复用器,这些数据是在不同时钟边沿发射数据的,具有延迟一个可变量的选择线,以调整选择,使得数据在所有端口上的多路复用器的输入处是干净的。