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1. 发明申请

US20080059952A1 Method for Replicating and Synchronizing a Plurality of Physical Instances with a Logical Master 失效
标题翻译：使用逻辑主机复制和同步多个物理实例的方法
公开(公告)号：US20080059952A1
公开(公告)日：2008-03-06
申请号：US11468031
申请日：2006-08-29
申请人： Gary A. Van Huben , David A. Webber , Christopher J. Berry
发明人： Gary A. Van Huben , David A. Webber , Christopher J. Berry
IPC分类号： G06F9/44
CPC分类号： G06F17/30575 , G06F11/2094
摘要： Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets. This permits all existing verification processes that are normally executed against the common data set to also be equally applied to the clones of said data set by way of automatic synchronization between of the common dataset and the clones.
摘要翻译：设计数据管理使用一个共同的数据集副本以及多个实例，同时继续利用现有的设计数据库和现有的CAD工具。允许最小量的用户干预来创建和维护公共数据集，设计数据管理使用将一般数据集复制到一个或多个克隆数据集中。该方法优选地提供用于复制和同步一个或多个数据集与主数据集，包括提供主数据集和至少一个克隆数据集的数据设计管理，以及将主物理设计数据集复制到一个或多个物理允许定制所述一个或多个物理实例的实例。主数据集描述了设计组件，电路宏和电路实体中的至少一个，并且包括逻辑数据集，并且它包括物理设计数据集。这允许通常针对公共数据集执行的所有现有验证过程也可以通过公共数据集和克隆之间的自动同步同样地应用于所述数据集的克隆。

2. 发明授权

US07735051B2 Method for replicating and synchronizing a plurality of physical instances with a logical master 失效
标题翻译：用于使用逻辑主机复制和同步多个物理实例的方法
公开(公告)号：US07735051B2
公开(公告)日：2010-06-08
申请号：US11468031
申请日：2006-08-29
申请人： Gary A. Van Huben , David A. Webber , Christopher J. Berry
发明人： Gary A. Van Huben , David A. Webber , Christopher J. Berry
IPC分类号： G06F17/50
CPC分类号： G06F17/30575 , G06F11/2094
摘要： Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets. This permits all existing verification processes that are normally executed against the common data set to also be equally applied to the clones of said data set by way of automatic synchronization between of the common dataset and the clones.
摘要翻译：设计数据管理使用一个共同的数据集副本以及多个实例，同时继续利用现有的设计数据库和现有的CAD工具。允许最小量的用户干预来创建和维护公共数据集，设计数据管理使用将一般数据集复制到一个或多个克隆数据集中。该方法优选地提供用于复制和同步一个或多个数据集与主数据集，包括提供主数据集和至少一个克隆数据集的数据设计管理，以及将主物理设计数据集复制到一个或多个物理允许定制所述一个或多个物理实例的实例。主数据集描述了设计组件，电路宏和电路实体中的至少一个，并且包括逻辑数据集，并且它包括物理设计数据集。这允许通常针对公共数据集执行的所有现有验证过程也可以通过公共数据集和克隆之间的自动同步同样地应用于所述数据集的克隆。

3. 发明授权

US08299610B1 Semiconductor device having RF shielding and method therefor 有权
标题翻译：具有RF屏蔽的半导体器件及其方法
公开(公告)号：US08299610B1
公开(公告)日：2012-10-30
申请号：US11971577
申请日：2008-01-09
申请人： Christopher J. Berry , Christopher M. Scanlan
发明人： Christopher J. Berry , Christopher M. Scanlan
IPC分类号： H01L23/12
CPC分类号： H01L23/552 , H01L23/13 , H01L23/29 , H01L23/3128 , H01L23/5389 , H01L24/48 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/81801 , H01L2224/83 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15159 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface of the substrate. A conductive coating is applied to the mold compound and to at least one metal layer exposed on at least one side surface of the substrate.
摘要翻译：半导体器件和制造方法具有具有多个金属层的衬底。至少一个金属层暴露在半导体器件的至少一个侧表面上。模具耦合到基板。模具化合物封装模具和衬底的顶表面。将导电涂层施加到模制化合物和暴露于基底的至少一个侧表面上的至少一个金属层。

4. 发明授权

US08283767B1 Dual laminate package structure with embedded elements 有权
标题翻译：双层压封装结构，嵌入式元件
公开(公告)号：US08283767B1
公开(公告)日：2012-10-09
申请号：US12964453
申请日：2010-12-09
申请人： Christopher J. Berry
发明人： Christopher J. Berry
IPC分类号： H01L23/02 , H01L23/04 , H01L23/26
CPC分类号： H01L21/561 , H01L23/3121 , H01L23/5385 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32013 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1041 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/3025 , H01L2924/00 , H01L2224/32145 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populate with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package.
摘要翻译：在这种底部基板之前或之后，安装并电连接到底部半导体封装基板的互连结构（即，插入器）填充有一个或多个电子部件。随后，也可以将一个或多个电子元件的顶部半导体封装基板安装到插入器上，使得所有电子部件都设置在顶部和底部插入件之间。此后，在顶部和底部基底之间注射合适的模制化合物，模制化合物围绕电子部件流动，在BGA接头之间，并且至少部分地围绕插入件，从而有助于将插入件锁定在完成的半导体封装中的适当位置。

5. 发明授权

US08261224B2 Computer program product, apparatus, and method for inserting components in a hierarchical chip design 有权
标题翻译：用于在分层芯片设计中插入组件的计算机程序产品，装置和方法
公开(公告)号：US08261224B2
公开(公告)日：2012-09-04
申请号：US12034644
申请日：2008-02-20
申请人： Frank Malgioglio , Christopher J. Berry
发明人： Frank Malgioglio , Christopher J. Berry
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Components are inserted into a cell-based current chin design with multiple levels of nested hierarchy. A selection of components having various silicon densities to insert into the current chip design is received. The components are inserted into the current chip design such that the components do not touch or overlap existing circuits or silicon shapes in the current chip design. The components are inserted such that components having highest silicon densities are placed further away from the existing circuits or silicon shapes than components having lower silicon densities.
摘要翻译：将组件插入到具有多级嵌套层次结构的基于单元格的当前下巴设计中。接收具有插入到当前芯片设计中的具有各种硅密度的组件的选择。将部件插入到当前芯片设计中，使得组件在当前芯片设计中不接触或重叠现有电路或硅形状。这些部件被插入，使得具有最高硅密度的部件被放置成远离现有的电路或硅形状，而不是具有较低硅密度的部件。

6. 发明授权

US07987400B2 Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy 有权
标题翻译：优化具有多层次结构的集成电路中的扫描链的方法
公开(公告)号：US07987400B2
公开(公告)日：2011-07-26
申请号：US12035500
申请日：2008-02-22
申请人： Christopher J. Berry , Lawrence David Curley , Patrick James Meaney , Diana Lynn Orf
发明人： Christopher J. Berry , Lawrence David Curley , Patrick James Meaney , Diana Lynn Orf
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318536
摘要： A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.
摘要翻译：一种用于优化集成电路中具有多层次层次结构的扫描链的方法，可以解决无限链和树桩，并分开所有其他链和树桩。通过将链包围的区域和残端的起始点和终点分成由多个网格框组成的网格，并且将网格框确定为网格框连接路由以访问所有网格框，来优化无限链和树桩的起始点和终点之间的网格框通过运行路由算法的计算机。优化的所有其他链和树桩被随机地分配给一个树桩，一个可以通过该树桩物理达到的链，并根据附加链中的锁存数，其物理位置和锁存数量向该残基添加一个附加链已分配

7. 发明授权

US07898066B1 Semiconductor device having EMI shielding and method therefor 有权
标题翻译：具有EMI屏蔽的半导体器件及其方法
公开(公告)号：US07898066B1
公开(公告)日：2011-03-01
申请号：US11754209
申请日：2007-05-25
申请人： Christopher M. Scanlan , Christopher J. Berry , Timothy L. Olson
发明人： Christopher M. Scanlan , Christopher J. Berry , Timothy L. Olson
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0655 , H01L25/0657 , H01L2224/2919 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/83101 , H01L2224/85 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/15311 , H01L2924/15313 , H01L2924/16195 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00014 , H01L2224/83 , H01L2924/0665 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a substrate having a plurality of metal layers. A die is coupled to the substrate. A plurality of metal wires is provided. At least one end of each of the metal wires is electrically coupled to at least one metal layer. A mold compound is used to encapsulate the die, a first surface of the substrate, and the plurality of metal wires. A portion of at least one metal wire remains exposed. A conductive coating is applied to the mold compound and to the portion of the at least one metal wire exposed.
摘要翻译：半导体器件具有具有多个金属层的衬底。模具耦合到基板。提供多根金属线。每个金属线的至少一端电耦合到至少一个金属层。模具化合物用于封装模具，衬底的第一表面和多个金属线。至少一根金属线的一部分保持暴露。将导电涂层施加到模具化合物和暴露的至少一种金属线的部分。

8. 发明授权

US07745910B1 Semiconductor device having RF shielding and method therefor 有权
标题翻译：具有RF屏蔽的半导体器件及其方法
公开(公告)号：US07745910B1
公开(公告)日：2010-06-29
申请号：US11775492
申请日：2007-07-10
申请人： Timothy L. Olson , Christopher M. Scanlan , Christopher J. Berry
发明人： Timothy L. Olson , Christopher M. Scanlan , Christopher J. Berry
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L21/561 , H01L23/3121 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/12044 , H01L2924/1433 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2224/85 , H01L2224/83 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a substrate comprising at least one dielectric layer and at least one metal layer on a first surface of the substrate. A die is attached to the first surface of the substrate. A mold compound is used to encapsulate the die and partially encapsulate the first surface of the substrate. The mold compound has a protrusion proximate to the at least one metal layer. A conductive material covers the mold compound, including the protrusion, and contacts the at least one metal layer.
摘要翻译：半导体器件具有包括至少一个电介质层和在该衬底的第一表面上的至少一个金属层的衬底。模具附接到基板的第一表面。模具化合物用于封装模具并且部分地封装衬底的第一表面。模具化合物具有靠近至少一个金属层的突起。导电材料覆盖包括突起的模具化合物，并接触至少一个金属层。

9. 发明授权

US07739538B2 Double data rate chaining for synchronous DDR interfaces 失效
标题翻译：双数据速率链接同步DDR接口
公开(公告)号：US07739538B2
公开(公告)日：2010-06-15
申请号：US11426651
申请日：2006-06-27
申请人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
发明人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
IPC分类号： G06F5/06 , G11C8/16
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译：一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。

10. 发明授权

US07681169B2 Process for managing complex pre-wired net segments in a VLSI design 有权
标题翻译：在VLSI设计中管理复杂的预先有线网段的过程
公开(公告)号：US07681169B2
公开(公告)日：2010-03-16
申请号：US11846577
申请日：2007-08-29
申请人： Christopher J. Berry , Michael A. Bowen , Michael R. Scheuermann , Michael H. Wood
发明人： Christopher J. Berry , Michael A. Bowen , Michael R. Scheuermann , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.
摘要翻译：使用烟道预先接线多层金属的方法包括以下步骤：接收包括烟道几何形状和烟道特性的信息; 生成针对流感的设计的多个路由模式; 识别要在设计中预先布线的宏实例终端; 在设计中选择用于宏实例终端的路由模式中的至少一个以避免阻塞; 并实例化设计，使得烟道可以被操纵为过孔。

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