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1. 发明授权

US06337834B1 Synchronous signal generation circuit 有权
标题翻译：同步信号发生电路
公开(公告)号：US06337834B1
公开(公告)日：2002-01-08
申请号：US09706842
申请日：2000-11-07
申请人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
发明人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/22 , G11C7/222
摘要： The present invention provides a synchronous signal generation circuit that can be operated with a high accuracy, at a high speed and with a low power consumption without being affected by the process dispersion. The synchronous signal generation circuit of the present invention comprises a real circuit including an input receiver, an off-chip driver, and a mirror-type synchronous circuit, and a dummy circuit for determining the delay time in the mirror-type synchronous circuit, the dummy circuit including an input receiver and an off-chip driver. In the dummy circuit, the input signal is supplied first to the off-chip driver and, then, to the input receiver so as to permit the signal between the off-chip driver and the input receiver to be a small amplitude signal. It follows that the real circuit and the dummy circuit are equal to each other in the signal levels in the input and output portions of each of the input receiver and the off-chip driver. The particular construction makes it possible to minimize the error in the delay time between the real circuit and the dummy circuit relative to the process dispersion so as to improve the synchronizing accuracy and, thus, to achieve a high speed I/O.
摘要翻译：本发明提供一种同步信号发生电路，其能够以高精度，高速度且低功耗地操作，而不受处理分散的影响。本发明的同步信号发生电路包括实际电路，其包括输入接收器，片外驱动器和反射镜型同步电路，以及用于确定镜式同步电路中的延迟时间的虚拟电路，虚拟电路包括输入接收器和片外驱动器。在虚拟电路中，首先将输入信号提供给片外驱动器，然后提供给输入接收器，以允许片外驱动器和输入接收器之间的信号为小振幅信号。因此，实际电路和虚拟电路在每个输入接收器和片外驱动器的输入和输出部分的信号电平中彼此相等。该特定结构使得可以将实际电路和虚拟电路之间相对于处理色散的延迟时间的误差最小化，从而提高同步精度，从而实现高速I / O。

2. 发明授权

US06608514B1 Clock signal generator circuit and semiconductor integrated circuit with the same circuit 失效
标题翻译：时钟信号发生器电路和半导体集成电路具有相同的电路
公开(公告)号：US06608514B1
公开(公告)日：2003-08-19
申请号：US09511352
申请日：2000-02-23
申请人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
发明人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
IPC分类号： H03K300
CPC分类号： G11C7/222 , G11C7/22 , H03K5/00006 , H03K5/135
摘要： A clock signal generator circuit comprises an off-chip driver, a first clock control circuit for outputting a first internal clock signal Tu synchronizing with an external clock signal CK, a second clock control circuit for outputting a second internal clock signal Td 180° out-of-phase with the external clock signal CK, a third clock control circuit for outputting a third internal clock signal aTx1 synchronizing with the first clock signal Tu and advanced in phase by at least the signal delay time in the off-chip driver, a fourth clock control circuit for outputting a fourth internal clock signal aTx2 synchronizing with the second clock signal Td and advanced in phase by at least the signal delay time in the off-chip driver, an OR circuit to which the third and fourth internal clock signals aTx1, aTx2 are inputted and which outputs a fifth internal clock signal aTx, and a fifth clock control circuit for outputting a sixth internal clock signal Tx which is in synchronization with the fifth internal clock signal aTx outputted from the OR circuit, has twice the frequency of the external clock signal CK, and is advanced in phase by the signal delay time in the off-chip driver.
摘要翻译：时钟信号发生器电路包括片外驱动器，用于输出与外部时钟信号CK同步的第一内部时钟信号Tu的第一时钟控制电路，用于将第二内部时钟信号Td 180°输出的第二时钟控制电路，与外部时钟信号CK的同相;第三时钟控制电路，用于输出与第一时钟信号Tu同步的第三内部时钟信号aTx1并至少在芯片外驱动器中的信号延迟时间相位前进;第四时钟控制电路，时钟控制电路，用于输出与第二时钟信号Td同步的第四内部时钟信号aTx2并至少在片外驱动器中的信号延迟时间相位前进;第三和第四内部时钟信号aTx1，输入aTx2并输出第五内部时钟信号aTx，以及第五时钟控制电路，用于输出与f同步的第六内部时钟信号Tx 从OR电路输出的第四内部时钟信号aTx具有外部时钟信号CK的两倍频率，并且在片外驱动器中相位提前信号延迟时间。

3. 发明授权

US06449212B1 Analog synchronization circuit for synchronizing external and internal clock signals 失效
标题翻译：模拟同步电路，用于同步外部和内部时钟信号
公开(公告)号：US06449212B1
公开(公告)日：2002-09-10
申请号：US09628449
申请日：2000-07-28
申请人： Haruki Toda , Hironobu Akita , Katsuaki Isobe
发明人： Haruki Toda , Hironobu Akita , Katsuaki Isobe
IPC分类号： G11C800
CPC分类号： H03L7/00 , H03K5/08 , H03K5/13 , H03K5/135
摘要： A first capacitor is charged by a constant current source circuit for a time corresponding to the delay time of forward pulses. A second capacitor is charged by a constant current source circuit. A comparator compares the voltages of the first and second capacitors, and outputs a timing signal when these voltages match. For this reason, a timing at which the second capacitor has been charged for a time corresponding to the delay time of backward pulses can be obtained.
摘要翻译：第一电容器由恒流源电路充电一段与正向脉冲的延迟时间对应的时间。第二电容器由恒流源电路充电。比较器比较第一和第二电容器的电压，并且当这些电压匹配时输出定时信号。因此，可以获得第二电容器已经对与反向脉冲的延迟时间相对应的时间的定时。

4. 发明授权

US06333658B1 Analog synchronization circuit 有权
标题翻译：模拟同步电路
公开(公告)号：US06333658B1
公开(公告)日：2001-12-25
申请号：US09707791
申请日：2000-11-08
申请人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe , Masaharu Wada , Haruki Toda
发明人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe , Masaharu Wada , Haruki Toda
IPC分类号： H03H1126
CPC分类号： H03K5/135
摘要： An analog synchronization circuit includes an input buffer which is supplied with an external clock signal, a delay monitor which is supplied with a clock signal output from the input buffer, an output buffer for outputting a clock signal synchronous with the external clock signal and two charge balance delay circuits. The two charge balance delay circuits are equivalent to delay lines in a mirror type delay locked loop. Each charge balance delay circuits operates once in two consecutive cycles of the external clock signal. The two charge balance delay circuits alternately operate and output signals of the charge balance delay circuits are supplied to the output buffer via an OR gate. First and second capacitors are provided in each charge balance delay circuits. A first current source circuit charges the first capacitor for a time equivalent to a delay time of a forward pulse. The second capacitor is charged by a second current source circuit. A comparator compares charge voltages of the first and second capacitors with each other and generates a timing signal when both charge voltages coincide with each other.
摘要翻译：模拟同步电路包括被提供有外部时钟信号的输入缓冲器，被提供有从输入缓冲器输出的时钟信号的延迟监视器，用于输出与外部时钟信号同步的时钟信号的输出缓冲器和两个充电平衡延迟电路。两个电荷平衡延迟电路等效于镜像延迟锁定环路中的延迟线。每个电荷平衡延迟电路在外部时钟信号的两个连续周期中运行一次。两个电荷平衡延迟电路交替工作，并且电荷平衡延迟电路的输出信号通过或门提供给输出缓冲器。在每个电荷平衡延迟电路中提供第一和第二电容器。第一电流源电路对第一电容器充电等于正向脉冲的延迟时间的时间。第二电容器由第二电流源电路充电。比较器将第一和第二电容器的充电电压彼此进行比较，并且当两个充电电压彼此一致时产生定时信号。

5. 发明授权

US08687406B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08687406B2
公开(公告)日：2014-04-01
申请号：US13597740
申请日：2012-08-29
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C13/0097 , G11C2213/71 , G11C2213/73
摘要： According to an embodiment, a semiconductor memory device comprises: a memory cell array configured having a plurality of memory cell mats, the memory cell mats including a plurality of first lines, second lines, and memory cells, and the memory cell mats being stacked such that the first and second lines are shared alternately by each of the memory cell mats; and a peripheral circuit. Each of the memory cells has a variable resistance characteristic and a current rectifying characteristic. An orientation from an anode toward a cathode of all the memory cells is identical. The peripheral circuit applies to one of the first line and the second line connected to an anode side of the selected memory cell a selected bit line voltage, and applies to the other a selected word line voltage.
摘要翻译：根据实施例，半导体存储器件包括：配置有多个存储单元垫的存储单元阵列，所述存储单元阵列包括多个第一行，第二行和存储单元，并且存储单元阵列被堆叠第一和第二行由每个存储单元垫交替共享; 和外围电路。每个存储单元具有可变电阻特性和电流整流特性。从所有存储器单元的阳极到阴极的取向是相同的。外围电路适用于与所选存储单元的阳极侧连接的选定位线电压的第一线路和第二线路中的一条线路，并且向另一条线路电压施加。

6. 发明申请

US20140009997A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140009997A1
公开(公告)日：2014-01-09
申请号：US14005149
申请日：2012-03-07
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C2013/0073 , G11C2213/71 , G11C2213/72 , H01L27/115
摘要： A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.
摘要翻译：一种半导体存储器件，包括存储单元阵列，所述存储单元阵列包括存储单元层，所述存储单元层包含多个用于根据不同电阻状态存储数据的存储单元; 以及访问电路，其操作以访问所述存储单元，所述存储单元在施加第一极性的电压时将所述电阻状态从第一电阻状态改变为第二电阻状态，并且从所述第二电阻状态改变所述电阻状态在施加第二极性的电压的情况下，所述存取电路将访问所述存储单元所需的电压施加到连接到所选择的存储单元的第一和第二行，并且使所述第一和第连接到未选择的存储器单元的第二行进入浮置状态以访问所选存储单元。

7. 发明授权

US08537595B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US08537595B2
公开(公告)日：2013-09-17
申请号：US13231687
申请日：2011-09-13
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C13/02
CPC分类号： G11C8/12 , G11C13/00 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line.
摘要翻译：一种电阻变化存储器件包括：具有层叠在其上的多层垫的单元阵列，每个垫具有彼此相交的字线和位线以及布置在其交叉处的电阻变化型存储单元，每个垫还具有其中参考单元和连接到参考单元的参考位线，参考单元设置为一定电阻值的状态; 选择电路，被配置为选择单元阵列的每个矩阵中的字线，并且同时选择与所选择的字线和参考位线相交的位线; 以及读出放大器，被配置为通过比较所选位线上的所选存储单元和参考位线上的参考单元的各个单元电流来检测数据。

8. 发明授权

US08400816B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US08400816B2
公开(公告)日：2013-03-19
申请号：US13237500
申请日：2011-09-20
申请人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
发明人： Haruki Toda , Hirofumi Inoue , Hiroto Nakai
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C5/063 , G11C8/14 , G11C11/56 , G11C13/0028 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.
摘要翻译：电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

9. 发明授权

US08315082B2 Resistance-changing memory device 有权
标题翻译：电阻变化存储器件
公开(公告)号：US08315082B2
公开(公告)日：2012-11-20
申请号：US13446137
申请日：2012-04-13
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0033 , G11C13/004 , G11C16/3431 , G11C2013/0047 , G11C2013/0054 , G11C2213/72
摘要： A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
摘要翻译：电阻变化存储器件具有存储单元的单元阵列，每个存储单元存储数据作为可逆设置的电阻值，用于从单元阵列中的选定存储单元读取数据的读出放大器，以及电压发生器电路，在读取所选择的存储单元的数据之后，根据读取的数据，产生用于收敛该选择的存储单元的电阻状态的电压脉冲。

10. 发明授权

US08237143B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US08237143B2
公开(公告)日：2012-08-07
申请号：US13217493
申请日：2011-08-25
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H01L29/02
CPC分类号： G11C13/0004 , G11C5/02 , G11C7/18 , G11C13/0007 , G11C2211/4013 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.
摘要翻译：存储器件具有半导体衬底; 多个单元阵列，堆叠在基板上方，每个单元阵列具有存储单元，每个通常连接沿着第一方向布置的多个单元的一端的位线和每个共同连接沿着第二方向布置的多个单元的另一端的字线; 在基板上形成的读/写电路，位于单元阵列下面; 第一和第二垂直布线沿着第一方向布置在每个单元阵列的两侧，以将位线连接到读/写电路; 以及在第二方向上设置在每个单元阵列两侧的第三垂直布线，以将字线连接到读/写电路。

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