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1. 发明授权

US06608514B1 Clock signal generator circuit and semiconductor integrated circuit with the same circuit 失效
标题翻译：时钟信号发生器电路和半导体集成电路具有相同的电路
公开(公告)号：US06608514B1
公开(公告)日：2003-08-19
申请号：US09511352
申请日：2000-02-23
申请人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
发明人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
IPC分类号： H03K300
CPC分类号： G11C7/222 , G11C7/22 , H03K5/00006 , H03K5/135
摘要： A clock signal generator circuit comprises an off-chip driver, a first clock control circuit for outputting a first internal clock signal Tu synchronizing with an external clock signal CK, a second clock control circuit for outputting a second internal clock signal Td 180° out-of-phase with the external clock signal CK, a third clock control circuit for outputting a third internal clock signal aTx1 synchronizing with the first clock signal Tu and advanced in phase by at least the signal delay time in the off-chip driver, a fourth clock control circuit for outputting a fourth internal clock signal aTx2 synchronizing with the second clock signal Td and advanced in phase by at least the signal delay time in the off-chip driver, an OR circuit to which the third and fourth internal clock signals aTx1, aTx2 are inputted and which outputs a fifth internal clock signal aTx, and a fifth clock control circuit for outputting a sixth internal clock signal Tx which is in synchronization with the fifth internal clock signal aTx outputted from the OR circuit, has twice the frequency of the external clock signal CK, and is advanced in phase by the signal delay time in the off-chip driver.
摘要翻译：时钟信号发生器电路包括片外驱动器，用于输出与外部时钟信号CK同步的第一内部时钟信号Tu的第一时钟控制电路，用于将第二内部时钟信号Td 180°输出的第二时钟控制电路，与外部时钟信号CK的同相;第三时钟控制电路，用于输出与第一时钟信号Tu同步的第三内部时钟信号aTx1并至少在芯片外驱动器中的信号延迟时间相位前进;第四时钟控制电路，时钟控制电路，用于输出与第二时钟信号Td同步的第四内部时钟信号aTx2并至少在片外驱动器中的信号延迟时间相位前进;第三和第四内部时钟信号aTx1，输入aTx2并输出第五内部时钟信号aTx，以及第五时钟控制电路，用于输出与f同步的第六内部时钟信号Tx 从OR电路输出的第四内部时钟信号aTx具有外部时钟信号CK的两倍频率，并且在片外驱动器中相位提前信号延迟时间。

2. 发明授权

US06449212B1 Analog synchronization circuit for synchronizing external and internal clock signals 失效
标题翻译：模拟同步电路，用于同步外部和内部时钟信号
公开(公告)号：US06449212B1
公开(公告)日：2002-09-10
申请号：US09628449
申请日：2000-07-28
申请人： Haruki Toda , Hironobu Akita , Katsuaki Isobe
发明人： Haruki Toda , Hironobu Akita , Katsuaki Isobe
IPC分类号： G11C800
CPC分类号： H03L7/00 , H03K5/08 , H03K5/13 , H03K5/135
摘要： A first capacitor is charged by a constant current source circuit for a time corresponding to the delay time of forward pulses. A second capacitor is charged by a constant current source circuit. A comparator compares the voltages of the first and second capacitors, and outputs a timing signal when these voltages match. For this reason, a timing at which the second capacitor has been charged for a time corresponding to the delay time of backward pulses can be obtained.
摘要翻译：第一电容器由恒流源电路充电一段与正向脉冲的延迟时间对应的时间。第二电容器由恒流源电路充电。比较器比较第一和第二电容器的电压，并且当这些电压匹配时输出定时信号。因此，可以获得第二电容器已经对与反向脉冲的延迟时间相对应的时间的定时。

3. 发明授权

US06337834B1 Synchronous signal generation circuit 有权
标题翻译：同步信号发生电路
公开(公告)号：US06337834B1
公开(公告)日：2002-01-08
申请号：US09706842
申请日：2000-11-07
申请人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
发明人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/22 , G11C7/222
摘要： The present invention provides a synchronous signal generation circuit that can be operated with a high accuracy, at a high speed and with a low power consumption without being affected by the process dispersion. The synchronous signal generation circuit of the present invention comprises a real circuit including an input receiver, an off-chip driver, and a mirror-type synchronous circuit, and a dummy circuit for determining the delay time in the mirror-type synchronous circuit, the dummy circuit including an input receiver and an off-chip driver. In the dummy circuit, the input signal is supplied first to the off-chip driver and, then, to the input receiver so as to permit the signal between the off-chip driver and the input receiver to be a small amplitude signal. It follows that the real circuit and the dummy circuit are equal to each other in the signal levels in the input and output portions of each of the input receiver and the off-chip driver. The particular construction makes it possible to minimize the error in the delay time between the real circuit and the dummy circuit relative to the process dispersion so as to improve the synchronizing accuracy and, thus, to achieve a high speed I/O.
摘要翻译：本发明提供一种同步信号发生电路，其能够以高精度，高速度且低功耗地操作，而不受处理分散的影响。本发明的同步信号发生电路包括实际电路，其包括输入接收器，片外驱动器和反射镜型同步电路，以及用于确定镜式同步电路中的延迟时间的虚拟电路，虚拟电路包括输入接收器和片外驱动器。在虚拟电路中，首先将输入信号提供给片外驱动器，然后提供给输入接收器，以允许片外驱动器和输入接收器之间的信号为小振幅信号。因此，实际电路和虚拟电路在每个输入接收器和片外驱动器的输入和输出部分的信号电平中彼此相等。该特定结构使得可以将实际电路和虚拟电路之间相对于处理色散的延迟时间的误差最小化，从而提高同步精度，从而实现高速I / O。

4. 发明授权

US06333658B1 Analog synchronization circuit 有权
标题翻译：模拟同步电路
公开(公告)号：US06333658B1
公开(公告)日：2001-12-25
申请号：US09707791
申请日：2000-11-08
申请人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe , Masaharu Wada , Haruki Toda
发明人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe , Masaharu Wada , Haruki Toda
IPC分类号： H03H1126
CPC分类号： H03K5/135
摘要： An analog synchronization circuit includes an input buffer which is supplied with an external clock signal, a delay monitor which is supplied with a clock signal output from the input buffer, an output buffer for outputting a clock signal synchronous with the external clock signal and two charge balance delay circuits. The two charge balance delay circuits are equivalent to delay lines in a mirror type delay locked loop. Each charge balance delay circuits operates once in two consecutive cycles of the external clock signal. The two charge balance delay circuits alternately operate and output signals of the charge balance delay circuits are supplied to the output buffer via an OR gate. First and second capacitors are provided in each charge balance delay circuits. A first current source circuit charges the first capacitor for a time equivalent to a delay time of a forward pulse. The second capacitor is charged by a second current source circuit. A comparator compares charge voltages of the first and second capacitors with each other and generates a timing signal when both charge voltages coincide with each other.
摘要翻译：模拟同步电路包括被提供有外部时钟信号的输入缓冲器，被提供有从输入缓冲器输出的时钟信号的延迟监视器，用于输出与外部时钟信号同步的时钟信号的输出缓冲器和两个充电平衡延迟电路。两个电荷平衡延迟电路等效于镜像延迟锁定环路中的延迟线。每个电荷平衡延迟电路在外部时钟信号的两个连续周期中运行一次。两个电荷平衡延迟电路交替工作，并且电荷平衡延迟电路的输出信号通过或门提供给输出缓冲器。在每个电荷平衡延迟电路中提供第一和第二电容器。第一电流源电路对第一电容器充电等于正向脉冲的延迟时间的时间。第二电容器由第二电流源电路充电。比较器将第一和第二电容器的充电电压彼此进行比较，并且当两个充电电压彼此一致时产生定时信号。

5. 发明授权

US06313674B1 Synchronizing circuit for generating internal signal synchronized to external signal 有权
标题翻译：同步电路，用于产生与外部信号同步的内部信号
公开(公告)号：US06313674B1
公开(公告)日：2001-11-06
申请号：US09641139
申请日：2000-08-16
申请人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe
发明人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe
IPC分类号： H03L706
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03K5/135 , H03L7/0812
摘要： A variable delay line outputs a clock signal advanced in phase by a time corresponding to a sum tH+tL of a time tH required to output high level data from an OCD circuit and a time tL required to output low level data from the OCD circuit. A replica circuit for outputting low level data has the same configuration as a circuit portion of the OCD circuit through which low level data passes. The replica circuit outputs a start signal SSH for outputting high level data from the OCD circuit. Another replica circuit for outputting high level data has the same configuration as a circuit portion of the OCD circuit through which high level data passes. The replica circuit outputs a start signal SSL for outputting low level data from the OCD circuit.
摘要翻译：可变延迟线输出相位提前的时钟信号与从OCD电路输出高电平数据所需的时间tH的和tH + tL和从OCD电路输出低电平数据所需的时间tL的时间。用于输出低电平数据的复制电路具有与低电平数据通过的OCD电路的电路部分相同的配置。复制电路输出用于从OCD电路输出高电平数据的启动信号SSH。用于输出高电平数据的另一复制电路具有与高电平数据通过的OCD电路的电路部分相同的配置。复制电路输出用于从OCD电路输出低电平数据的起始信号SSL。

6. 发明授权

US06359480B1 Synchronizing circuit for generating a signal synchronizing with a clock signal 失效
公开(公告)号：US06359480B1
公开(公告)日：2002-03-19
申请号：US09505204
申请日：2000-02-16
申请人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
发明人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
IPC分类号： H03L700
CPC分类号： H03K5/135 , H03K5/133 , H03L7/00
摘要： A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.

7. 发明授权

US06731149B2 Synchronizing circuit for generating a signal synchronizing with a clock signal 失效
标题翻译：用于产生与时钟信号同步的信号的同步电路
公开(公告)号：US06731149B2
公开(公告)日：2004-05-04
申请号：US10003312
申请日：2001-12-06
申请人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
发明人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
IPC分类号： H03K501
CPC分类号： H03K5/135 , H03K5/133 , H03L7/00
摘要： A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.
摘要翻译：用于正向脉冲的第一延迟线和用于反向脉冲的第二延迟线由单位延迟元件组成。状态保持部根据沿着第一延迟线传送的正向脉冲的传送位置来确定第二延迟线上的反向脉冲的输入位置。在构成第一和第二延迟线的单位延迟元件中，可以通过增加与脉冲信号的上升相关的晶体管的电流驱动能力来提高同步精度。

8. 发明授权

US06339345B1 Semiconductor device equipped with output circuit adjusting duration of high and low levels 有权
标题翻译：半导体器件配备有输出电路调节持续时间的高低电平
公开(公告)号：US06339345B1
公开(公告)日：2002-01-15
申请号：US09696048
申请日：2000-10-26
申请人： Satoshi Eto , Hironobu Akita , Katsuaki Isobe
发明人： Satoshi Eto , Hironobu Akita , Katsuaki Isobe
IPC分类号： H03L700
CPC分类号： G11C7/1066 , G11C7/1072 , G11C7/222 , G11C2207/2254 , H03K5/135 , H03K19/00384 , H03L7/00
摘要： In an output circuit 10, a latch circuit 11, a phase difference controlled circuit 12 and an output buffer circuit 13 are cascaded and a DATA is clocked into the latch circuit 11. A replica circuit 20 is a down-scaled version of a layout pattern of the output circuit 10, comprises circuits 21 to 23 corresponding to the circuits 11, 12 and 13, and a CLK is provided through a delay circuit 5 and a divide-by-2 frequency divider 16 to the data input of the latch circuit 21 as a data. The output of the replica circuit 20 is provided through a dummy load circuit 24 and a low pass filter 25 to a comparator 26, the output thereof is compared with a reference voltage Vref to generate count-up or count-down pulses. The pulses are counted by an up-down counter 27 whose count is provided to the phase difference controlled circuit 12 and its replica 22 to reduce the phase difference between rising and falling edges of the output signal of the output buffer circuit 23.
摘要翻译：在输出电路10中，锁存电路11，相位差控制电路12和输出缓冲器电路13级联，并且DATA被锁定到锁存电路11中。复制电路20是布局模式的缩小版本输出电路10包括对应于电路11,12和13的电路21至23，并且通过延迟电路5和分频2分频器16将CLK提供给锁存电路21的数据输入作为数据。复制电路20的输出通过虚拟负载电路24和低通滤波器25提供给比较器26，其输出与参考电压Vref进行比较，以产生递增计数或递减计数脉冲。脉冲由计数器27计数，该计数器的计数被提供给相位差控制电路12及其副本22，以减小输出缓冲电路23的输出信号的上升沿和下降沿之间的相位差。

9. 发明授权

US08315110B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US08315110B2
公开(公告)日：2012-11-20
申请号：US13315967
申请日：2011-12-09
申请人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C7/10
摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

10. 发明申请

US20110235417A1 NAND FLASH MEMORY 审中-公开
标题翻译： NAND闪存
公开(公告)号：US20110235417A1
公开(公告)日：2011-09-29
申请号：US13154522
申请日：2011-06-07
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C16/02
CPC分类号： G11C8/08 , G11C8/10 , G11C16/0483
摘要： A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state.
摘要翻译：在选择的位线和非选择的位线彼此相邻时读取的NAND快闪存储器具有存储单元阵列，其具有多个块，每个块由多个存储单元单元组成，每个块由多个存储单元单元组成所述存储单元具有多个电可重写存储单元，它们彼此连接并且由形成在p型半导体衬底中的n型阱围绕的p型阱组成，每个漏极侧选择栅晶体管其将存储单元单元连接到位线并连接到其栅极处的漏极侧选择栅极线，以及源极选择栅极晶体管，每个源极选择栅极晶体管将存储单元单元连接到源极线并连接到源极选择栅极线; 连接到所述存储单元阵列的字线，漏极侧选择栅极线和源极侧栅极线的行解码器，并将信号电压施加到字线，漏极侧选择栅极线和源极侧选择栅极线，所述存储单元阵列的侧栅极线用于选择块; 以及由列解码器控制并从所述存储单元阵列的所述位线进行选择的读出放大器，其中，在未被所述行解码器选择的块中，由所述读出放大器选择的所述位线被充电漏极侧选择栅极线，源极侧选择栅极线和p型半导体衬底设置为接地电位的状态，源极线，n型阱，p型阱和a 未被所述读出放大器选择的位线处于浮置状态。

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