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1. 发明授权

US06608514B1 Clock signal generator circuit and semiconductor integrated circuit with the same circuit 失效
标题翻译：时钟信号发生器电路和半导体集成电路具有相同的电路
公开(公告)号：US06608514B1
公开(公告)日：2003-08-19
申请号：US09511352
申请日：2000-02-23
申请人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
发明人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
IPC分类号： H03K300
CPC分类号： G11C7/222 , G11C7/22 , H03K5/00006 , H03K5/135
摘要： A clock signal generator circuit comprises an off-chip driver, a first clock control circuit for outputting a first internal clock signal Tu synchronizing with an external clock signal CK, a second clock control circuit for outputting a second internal clock signal Td 180° out-of-phase with the external clock signal CK, a third clock control circuit for outputting a third internal clock signal aTx1 synchronizing with the first clock signal Tu and advanced in phase by at least the signal delay time in the off-chip driver, a fourth clock control circuit for outputting a fourth internal clock signal aTx2 synchronizing with the second clock signal Td and advanced in phase by at least the signal delay time in the off-chip driver, an OR circuit to which the third and fourth internal clock signals aTx1, aTx2 are inputted and which outputs a fifth internal clock signal aTx, and a fifth clock control circuit for outputting a sixth internal clock signal Tx which is in synchronization with the fifth internal clock signal aTx outputted from the OR circuit, has twice the frequency of the external clock signal CK, and is advanced in phase by the signal delay time in the off-chip driver.
摘要翻译：时钟信号发生器电路包括片外驱动器，用于输出与外部时钟信号CK同步的第一内部时钟信号Tu的第一时钟控制电路，用于将第二内部时钟信号Td 180°输出的第二时钟控制电路，与外部时钟信号CK的同相;第三时钟控制电路，用于输出与第一时钟信号Tu同步的第三内部时钟信号aTx1并至少在芯片外驱动器中的信号延迟时间相位前进;第四时钟控制电路，时钟控制电路，用于输出与第二时钟信号Td同步的第四内部时钟信号aTx2并至少在片外驱动器中的信号延迟时间相位前进;第三和第四内部时钟信号aTx1，输入aTx2并输出第五内部时钟信号aTx，以及第五时钟控制电路，用于输出与f同步的第六内部时钟信号Tx 从OR电路输出的第四内部时钟信号aTx具有外部时钟信号CK的两倍频率，并且在片外驱动器中相位提前信号延迟时间。

2. 发明授权

US06433619B1 Pump circuit boosting a supply voltage 有权
公开(公告)号：US06433619B1
公开(公告)日：2002-08-13
申请号：US09972905
申请日：2001-10-10
申请人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
发明人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
IPC分类号： G05F110
摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.

3. 发明授权

US06326834B1 Pump circuit boosting a supply voltage 失效
标题翻译：泵电路提升电源电压
公开(公告)号：US06326834B1
公开(公告)日：2001-12-04
申请号：US09602896
申请日：2000-06-23
申请人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
发明人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
IPC分类号： G05F110
CPC分类号： H02M3/073
摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.
摘要翻译：用于对多个电容器的各个侧面节点进行充电的第一晶体管分别连接到电容器的这些节点。用于输出每个电容器的电荷的第二晶体管分别连接在电容器的相应的一个侧面节点和输出端子之间。用于将电容器的另一侧节点的电荷转移到其他节点的多个第三晶体管连接到相应的其他节点。每个电容器的电荷通过顺序地控制第三晶体管，通过一个路径从高电位的节点被串行地传递到较低电位的节点，或者每个电容器的电荷在高电位的任意节点之间并行传送潜在和低节点通过多个路径。通过这些操作，每个电容器的电荷被再循环。

4. 发明授权

US06438059B2 Fuse programming circuit for programming fuses 失效
标题翻译：用于编程保险丝的保险丝编程电路
公开(公告)号：US06438059B2
公开(公告)日：2002-08-20
申请号：US09874208
申请日：2001-06-06
申请人： Hironobu Akita , Kenji Tsuchida
发明人： Hironobu Akita , Kenji Tsuchida
IPC分类号： G11C700
CPC分类号： H01L27/0817
摘要： A fuse is programmed by being supplied with a current. The fuse is connected to a thyristor. A control circuit is connected to the gate of the thyristor. The control circuit turns the thyristor ON to allow the fuse to be programmed.
摘要翻译：通过提供电流来编程保险丝。保险丝连接到晶闸管。控制电路连接到晶闸管的栅极。控制电路将晶闸管导通，以使熔丝被编程。

5. 发明授权

US06452833B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06452833B2
公开(公告)日：2002-09-17
申请号：US09773606
申请日：2001-02-02
申请人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
发明人： Hironobu Akita , Kenji Tsuchida , Fumihiro Kohno
IPC分类号： G11C1124
CPC分类号： G11C7/12 , G11C11/4094
摘要： A BL kicker circuit includes first capacitors each of which is connected at one end to a first bit line which is one of bit lines of a corresponding pair and commonly connected at the other end, second capacitors each of which is connected at one end to a second bit line which is the other one of the bit lines of a corresponding pair and commonly connected at the other end, a first driver circuit having an output node for a first signal connected to the common connection node of the other ends of the first capacitors, a second drive circuit having an output node for a second signal connected to the common connection node of the other ends of the second capacitors, and a switch circuit used as an equalizing circuit connected between the output node for the first signal and the output node for the second signal.
摘要翻译： BL激光电路包括第一电容器，每个电容器的一端连接到第一位线，第一位线是相应对的位线之一，并且在另一端共同连接，第二电容器的一端连接到一端第二位线，其是相应对中的另一个位线并且在另一端共同连接，第一驱动器电路具有用于连接到第一电容器的另一端的公共连接节点的第一信号的输出节点具有连接到第二电容器的另一端的公共连接节点的第二信号的输出节点的第二驱动电路和用作连接在第一信号的输出节点和输出节点之间的均衡电路的开关电路对于第二个信号。

6. 发明授权

US06480423B2 High-speed cycle clock-synchronous memory device 失效
标题翻译：高速循环时钟同步存储器件
公开(公告)号：US06480423B2
公开(公告)日：2002-11-12
申请号：US09873313
申请日：2001-06-05
申请人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
发明人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4087
摘要： A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S≧N≧F.
摘要翻译：高速时钟同步存储装置设置有由单元阵列之间和单元阵列之间共享的读出放大器S / A和单元阵列控制器单元CNTRLi，其中与时钟同步的数据/命令的输入和输出访问命令提供所有同时地址数据位（行和列）。通过确认在两个连续命令之间观察到的位的改变，关于配置访问地址的一些地址位，设备判断当前访问是在与先前的访问相同的单元阵列之间，相邻单元阵列之间，还是在远程单元阵列。根据判断，应用适当的命令循环。此时，命令循环满足关系：S> = N> = F。

7. 发明授权

US06442088B1 Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory 失效
标题翻译：半导体存储器系统以及半导体存储器和半导体存储器的访问控制方法
公开(公告)号：US06442088B1
公开(公告)日：2002-08-27
申请号：US09986658
申请日：2001-11-09
申请人： Kenji Tsuchida , Haruki Toda
发明人： Kenji Tsuchida , Haruki Toda
IPC分类号： G11C700
CPC分类号： G11C11/4094 , G11C7/1072 , G11C7/12 , G11C7/22 , G11C2207/002
摘要： In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted, and a third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for the semiconductor chip size.
摘要翻译：在半导体存储器系统中，SDRAM包括被分成多个单元阵列块的存储单元阵列101，列解码器，行解码器和读出放大器电路。在SDRAM中，当进行单元阵列块中的连续访问时，设置具有第一周期时间的第一操作模式，当覆盖单元阵列的连续访问时，设置具有比第一周期时间短的第二周期时间的第二操作模式进行彼此分离的块，并且进行覆盖彼此相邻的单元阵列块的连续访问时，设定具有中等周期时间的第三操作模式。利用上述结构，可以在不设置特定的附件电路的同时抑制半导体芯片尺寸的开销来实现高速访问。

8. 发明授权

US06295231B1 High-speed cycle clock-synchronous memory device 失效
标题翻译：高速循环时钟同步存储器件
公开(公告)号：US06295231B1
公开(公告)日：2001-09-25
申请号：US09354102
申请日：1999-07-15
申请人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
发明人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4087
摘要： A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between two successive commands, regarding some of address bits configuring access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgement, suitable command cycle is applied. At this time, the command cycle satisfies relationship: S≧N≧F.
摘要翻译：高速时钟同步存储装置设置有由单元阵列之间和单元阵列之间共享的读出放大器S / A和单元阵列控制器单元CNTRLi，其中与时钟同步的数据/命令的输入和输出访问命令提供所有同时地址数据位（行和列）。通过确认在两个连续命令之间观察到的位的变化，关于配置访问地址的一些地址位，设备判断当前访问是在与先前访问相同的单元阵列之间，相邻单元阵列之间还是在远程单元之间阵列根据判断，应用适当的命令循环。此时，命令循环满足关系：S> = N> = F。

9. 发明授权

US06256258B1 Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory 失效
标题翻译：半导体存储器系统以及半导体存储器和半导体存储器的访问控制方法
公开(公告)号：US06256258B1
公开(公告)日：2001-07-03
申请号：US09411373
申请日：1999-10-04
申请人： Kenji Tsuchida , Haruki Toda
发明人： Kenji Tsuchida , Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C11/4094 , G11C7/1072 , G11C7/12 , G11C7/22 , G11C2207/002
摘要： In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted, and third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, a high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for the semiconductor chip size.
摘要翻译：在半导体存储器系统中，SDRAM包括被分成多个单元阵列块的存储单元阵列101，列解码器，行解码器和读出放大器电路。在SDRAM中，当进行单元阵列块中的连续访问时，设置具有第一周期时间的第一操作模式，当覆盖单元阵列的连续访问时，设置具有比第一周期时间短的第二周期时间的第二操作模式进行彼此分离的块，并且进行覆盖彼此相邻的单元阵列块的连续访问时，设定具有中等周期时间的第三操作模式。利用上述结构，可以在不设置特定附件电路的同时抑制半导体芯片尺寸的开销来实现高速访问。

10. 发明授权

US06647478B2 Semiconductor memory device 失效
公开(公告)号：US06647478B2
公开(公告)日：2003-11-11
申请号：US10175085
申请日：2002-06-20
申请人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
发明人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
IPC分类号： G06F1202
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of the read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.

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