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1. 发明授权

US07566946B2 Precision passive circuit structure 失效
标题翻译：精密无源电路结构
公开(公告)号：US07566946B2
公开(公告)日：2009-07-28
申请号：US11865432
申请日：2007-10-01
申请人： Douglas D. Coolbaugh , Hayden C. Cranford, Jr. , Terence B. Hook , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Hayden C. Cranford, Jr. , Terence B. Hook , Anthony K. Stamper
IPC分类号： H01C10/00
CPC分类号： H01L27/0802 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.
摘要翻译：在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个具有高于目标值的值，并且具有低于目标值的值。每个无源电路元件还具有与其串联的保险丝。还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择元素。

2. 发明授权

US08729908B2 Static noise margin monitoring circuit and method 有权
标题翻译：静态噪声容限监控电路及方法
公开(公告)号：US08729908B2
公开(公告)日：2014-05-20
申请号：US13407822
申请日：2012-02-29
申请人： Hayden C. Cranford, Jr. , Terence B. Hook
发明人： Hayden C. Cranford, Jr. , Terence B. Hook
IPC分类号： G01R29/26
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/0409 , G11C2029/5002
摘要： A monitoring circuit and method, wherein a voltage waveform having a linear falling edge is applied to a first node of at least one test memory cell (e.g., a plurality of test memory cells connected in parallel). The input voltage at the first node is captured when the output voltage at a second node of the test memory cell(s) rises above a high reference voltage during the falling edge. Then, a difference is determined between the input voltage as captured and either (1) the output voltage at the second node, as captured when the input voltage at the first node falls below the first reference voltage during the falling edge, or (2) a low reference voltage. This difference is proportional to the static noise margin (SNM) of the test memory cell(s) such that any changes in the difference noted with repeated monitoring are indicative of corresponding changes in the SNM.
摘要翻译：一种监视电路和方法，其中具有线性下降沿的电压波形被施加到至少一个测试存储器单元（例如，并联连接的多个测试存储单元）的第一节点。当在下降沿期间，当测试存储单元的第二个节点处的输出电压上升到高于参考电压时，捕获第一节点处的输入电压。然后，在捕获的输入电压和（1）第二节点处的输出电压之间确定差异，如在第一节点处的输入电压在下降沿期间低于第一参考电压时捕获的，或者（2）低参考电压。该差异与测试存储器单元的静态噪声容限（SNM）成比例，使得通过重复监测指出的差异中的任何变化表示SNM的相应变化。

3. 发明授权

US08416009B2 Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip 有权
标题翻译：用于在非常薄的绝缘体上（ETSOI）集成电路芯片上控制体偏置的解决方案
公开(公告)号：US08416009B2
公开(公告)日：2013-04-09
申请号：US13181754
申请日：2011-07-13
申请人： Hayden C. Cranford, Jr. , Terence B. Hook
发明人： Hayden C. Cranford, Jr. , Terence B. Hook
IPC分类号： H01L27/12
CPC分类号： G05F1/10 , H01L27/092 , H01L27/1203
摘要： Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.
摘要翻译：公开了用于优化跨越ETSOI设备的衬底的体偏压的解决方案。在一个实施例中，公开了一种用于优化跨越ETSOI设备的衬底的体偏压的装置，包括：用于感测至少一个预定电路参数的感测电路; 用于向ETSOI装置的基板施加偏置电压的充电电路; 以及连接到所述感测电路和所述充电电路的处理电路，所述处理电路被配置为接收所述感测电路的输出，并且响应于确定所述偏置电压是否偏离所述偏置电压而调整施加到所述ETSOI器件的衬底的偏置电压目标金额。

4. 发明授权

US07300807B2 Structure and method for providing precision passive elements 失效
标题翻译：提供精密无源元件的结构和方法
公开(公告)号：US07300807B2
公开(公告)日：2007-11-27
申请号：US10709109
申请日：2004-04-14
申请人： Douglas D Coolbaugh , Hayden C. Cranford, Jr. , Terence B. Hook , Anthony K. Stamper
发明人： Douglas D Coolbaugh , Hayden C. Cranford, Jr. , Terence B. Hook , Anthony K. Stamper
IPC分类号： H01L21/66
CPC分类号： H01L27/0802 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.
摘要翻译：在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个具有高于目标值的值，并且具有低于目标值的值。每个无源电路元件还具有与其串联的保险丝。还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择元素。

5. 发明授权

US07809054B2 One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效
标题翻译：单采样每位决策反馈均衡器（DFE）时钟和数据恢复
公开(公告)号：US07809054B2
公开(公告)日：2010-10-05
申请号：US11405997
申请日：2006-04-18
申请人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译：公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。输入电压被转换为电流并连接到电流求和节点。由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。另外，总和电流被积分并转换成电压。采样器用于基于所得到的电压进行位决定。采样后，积分器在分析下一位之前被复位。通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

6. 发明授权

US07755420B2 Intrinsic RC power distribution for noise filtering of analog supplies 失效
标题翻译：用于模拟电源噪声滤波的本征RC功率分配
公开(公告)号：US07755420B2
公开(公告)日：2010-07-13
申请号：US12196718
申请日：2008-08-22
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

7. 发明授权

US07721134B2 Method for on-chip diagnostic testing and checking of receiver margins 失效
标题翻译：用于片上诊断测试和接收器边距检查的方法
公开(公告)号：US07721134B2
公开(公告)日：2010-05-18
申请号：US11566576
申请日：2006-12-04
申请人： Hayden C. Cranford, Jr. , Daniel J. Friedman , Mounir Meghelli , Thomas H. Toifl
发明人： Hayden C. Cranford, Jr. , Daniel J. Friedman , Mounir Meghelli , Thomas H. Toifl
IPC分类号： H04L25/00 , H03D3/24
CPC分类号： G01R31/3171 , B82Y25/00 , G01R33/093
摘要： A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.
摘要翻译：提出了一种用于在诊断测试期间确定接收机系统的眼图边缘参数的方法和系统。接收机前端的电路包括一系列锁存器，XOR门和OR门，它们首先提供数据样本和边缘采样，即在（边沿）时钟的上升沿或下降沿采样的数据，其特征在于相位延迟相对到数据采样时钟。接收机还包括用于边缘时钟（边缘）与数据边缘的理想对准的优化电路。该方法还提供了边缘时钟从理想/锁定位置向左和向右移相以屏蔽数据眼图，以便计算误码率（BER）值。边缘时钟相对于数据采样时钟的位置决定了计算的BER的水平眼睛开度。

8. 发明授权

US07684478B2 Generating an eye diagram of integrated circuit transmitted signals 失效
标题翻译：生成集成电路传输信号的眼图
公开(公告)号：US07684478B2
公开(公告)日：2010-03-23
申请号：US11427831
申请日：2006-06-30
申请人： Hayden C. Cranford, Jr. , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford, Jr. , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： H04B17/00 , H04L27/06
CPC分类号： G01R31/31711 , H04L1/205 , H04L1/24
摘要： A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.
摘要翻译：通过在具有未知周期TS的IC上以嵌入的采样时钟采样，数字化和存储数据信号的电压采样来生成发送数据信号的K个电压样本的序列。 K电压样本相对于K次顺序TB [K]的时基绘制，归一化，所以所有采样都落在用于生成数据信号的数据时钟或单位时间为1的一个周期内。时基是通过估计采样时钟周期TSE为1 / P的某个倍数，其中P大于K.眼图分析时间抖动，其中只保存抖动的最小值。 TSE递增1 / P，直到TS大于数据时钟周期的一半。 TSE具有最小时间抖动的眼图用于分析数据通道。

9. 发明授权

US07661052B2 Using statistical signatures for testing high-speed circuits 失效
标题翻译：使用统计特征来测试高速电路
公开(公告)号：US07661052B2
公开(公告)日：2010-02-09
申请号：US12021950
申请日：2008-01-29
申请人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
IPC分类号： G06F11/277 , G06F11/16
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译：公开了一种用于测试高速电路的方法和系统。该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。因此，可以确定高速电路是否在期望的参数内起作用。

10. 发明授权

US07522000B2 Design structure for a serial link output stage differential amplifier 失效
标题翻译：串行输出级差分放大器的设计结构
公开(公告)号：US07522000B2
公开(公告)日：2009-04-21
申请号：US12114984
申请日：2008-05-05
申请人： Carrie E. Cox , Hayden C. Cranford, Jr.
发明人： Carrie E. Cox , Hayden C. Cranford, Jr.
IPC分类号： H03F3/45
CPC分类号： H03F1/523 , H03F1/52 , H03F3/45183 , H03F3/45632 , H03F2203/45244 , H03F2203/45342 , H03F2203/45456 , H03F2203/45466 , H03F2203/45702
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exceed desirable levels is provided by limiting the voltage across any two device terminals under power down conditions.
摘要翻译：一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试设计，用于传输由具有有限的最大电压容限的薄氧化物晶体管形成的差分放大器所需的较高幅度输出，这些最小电压容限符合通信协议标准要求处理电压，在转换期间，可以通过在断电条件下限制任何两个器件端子上的电压来提供所需的电平。

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