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1. 发明授权

US07834692B2 Peak detector with active ripple suppression 有权
标题翻译：具有主动纹波抑制的峰值检测器
公开(公告)号：US07834692B2
公开(公告)日：2010-11-16
申请号：US11856691
申请日：2007-09-17
申请人： Hyeon Min Bae , Naresh Shanbhag , Jonathan B. Ashbrook
发明人： Hyeon Min Bae , Naresh Shanbhag , Jonathan B. Ashbrook
IPC分类号： H03F3/45 , G01R19/04
CPC分类号： H03K5/1532
摘要： A peak detector circuit that responds rapidly to power transients, and yet is able to avoid interpreting data fluctuations as power transients by generating dual peak signals from an amplifier's differential output signal, where the dual peak signals have data ripple components that tend to cancel one another. The system and methods permit the peak detectors to be much more responsive to power transients by expanding their bandwidth (shortening the time constants) to the point that low frequency data components affect the individual peak detector signals, but the effects are cancelled out when the individual components are added together. The peak detector described herein may be used in an AGC system to provide ripple-free gain control signals, while rapidly following any power transients in transmitted signals.
摘要翻译：峰值检测器电路可以快速响应功率瞬变，并且能够通过从放大器的差分输出信号产生双峰值信号来避免将数据波动解释为功率瞬变，其中双峰值信号具有倾向于彼此抵消的数据波动分量。该系统和方法允许峰值检测器通过将其带宽（缩短时间常数）扩大到低频数据分量影响各个峰值检测器信号的程度来对功率瞬态响应更大，但是当个体组件添加在一起。本文描述的峰值检测器可用于AGC系统中，以在快速跟随发射信号中的任何功率瞬变之后提供无纹波增益控制信号。

2. 发明授权

US07695085B2 Variable gain amplifier having variable gain DC offset loop 有权
标题翻译：具有可变增益DC偏移环路的可变增益放大器
公开(公告)号：US07695085B2
公开(公告)日：2010-04-13
申请号：US11856680
申请日：2007-09-17
申请人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Jonathan B. Ashbrook
发明人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Jonathan B. Ashbrook
IPC分类号： B41J29/38 , H03F3/45
CPC分类号： H03F3/45098 , H03F3/45085 , H03F3/45179 , H03F3/45475 , H03F3/45968 , H03F2203/45138 , H03F2203/45506 , H03F2203/45521 , H03F2203/45722 , H03F2203/45728
摘要： A variable gain amplifier and offset cancellation loop circuit and methods for tracking and correcting DC offset errors that may vary in accordance with the gain of the variable gain amplifier. The circuit is designed to provide tracking of rapid changes in the offset error while maintaining a desired overall frequency response of the combined variable gain amplifier and offset loop. The offset loop cancellation circuit has a wide enough bandwidth to allow the offset cancellation loop to track rapid changes in offset errors that result from rapid changes to the amplifier's gain setting. A control circuit is provided to prevent the large offset cancellation loop bandwidth from having a detrimental effect on the amplifier's overall bandwidth when the amplifier is set to high levels of forward gain by adjusting the offset cancellation loop gain as the forward gain of the amplifier is altered.
摘要翻译：可变增益放大器和偏移消除环路电路以及跟踪和校正可能根据可变增益放大器的增益而变化的直流偏移误差的方法。该电路被设计为提供对偏移误差的快速变化的跟踪，同时保持组合的可变增益放大器和偏移环路的期望的总体频率响应。偏移回路消除电路具有足够宽的带宽，以允许偏移消除环路跟踪由放大器的增益设置的快速变化导致的偏移误差的快速变化。提供控制电路以防止大的偏移消除环路带宽对放大器的整体带宽产生不利影响，当放大器被设置为高电平的正向增益时，通过调整偏移消除环路增益，因为放大器的正向增益被改变。

3. 发明授权

US07592869B2 Variable gain amplifier having dual gain control 有权
标题翻译：具有双增益控制的可变增益放大器
公开(公告)号：US07592869B2
公开(公告)日：2009-09-22
申请号：US11856681
申请日：2007-09-17
申请人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Jonathan B. Ashbrook
发明人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Jonathan B. Ashbrook
IPC分类号： H03F3/45
CPC分类号： H03F1/3211 , H03F3/45098 , H03F2203/45506 , H03F2203/45722 , H03F2203/45728 , H03G1/0023
摘要： An electronic amplifier circuit that provides improved gain control linearity characteristics resulting from having a controllable field effect transistor (FET) acting as a degeneration resistance (degeneration resistance FET) and a controllable load resistance FET. The overall gain function of the amplifier exhibits improved linearity in part due to the presence of the load FET, which tends to cancel the nonlinear behavior emanating from the degeneration FET. The circuit also includes a control circuit for generating non-linear control signals that are responsive to process characteristics of the FETs, such that the degeneration resistance FET and load resistance FETs may be controlled more consistently and independently from process variations.
摘要翻译：一种电子放大器电路，其提供由具有用作退化电阻（退化电阻FET）和可控负载电阻FET的可控场效应晶体管（FET）引起的改善的增益控制线性特性。由于负载FET的存在，放大器的总体增益函数部分地呈现出改善的线性度，这倾向于消除从退化FET发出的非线性行为。该电路还包括用于产生响应于FET的工艺特性的非线性控制信号的控制电路，使得可以更一致地且独立于过程变化来控制退化电阻FET和负载电阻FET。

4. 发明申请

US20090072904A1 Variable Gain Amplifier Having Dual Gain Control 有权
标题翻译：具有双增益控制的可变增益放大器
公开(公告)号：US20090072904A1
公开(公告)日：2009-03-19
申请号：US11856681
申请日：2007-09-17
申请人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Jonathan B. Ashbrook
发明人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Jonathan B. Ashbrook
IPC分类号： H03F3/45
CPC分类号： H03F1/3211 , H03F3/45098 , H03F2203/45506 , H03F2203/45722 , H03F2203/45728 , H03G1/0023
摘要： An electronic amplifier circuit that provides improved gain control linearity characteristics resulting from having a controllable field effect transistor (FET) acting as a degeneration resistance (degeneration resistance FET) and a controllable load resistance FET. The overall gain function of the amplifier exhibits improved linearity in part due to the presence of the load FET, which tends to cancel the nonlinear behavior emanating from the degeneration FET. The circuit also includes a control circuit for generating non-linear control signals that are responsive to process characteristics of the FETs, such that the degeneration resistance FET and load resistance FETs may be controlled more consistently and independently from process variations.
摘要翻译：一种电子放大器电路，其提供由具有用作退化电阻（退化电阻FET）和可控负载电阻FET的可控场效应晶体管（FET）引起的改善的增益控制线性特性。由于负载FET的存在，放大器的总体增益函数部分地呈现出改善的线性度，这倾向于消除从退化FET发出的非线性行为。该电路还包括用于产生响应于FET的工艺特性的非线性控制信号的控制电路，使得可以更一致地且独立于过程变化来控制退化电阻FET和负载电阻FET。

5. 发明申请

US20090219008A1 PHASE DETECTOR UTILIZING ANALOG-TO-DIGITAL CONVERTER COMPONENTS 有权
标题翻译：相位检测器利用模拟数字转换器组件
公开(公告)号：US20090219008A1
公开(公告)日：2009-09-03
申请号：US12039424
申请日：2008-02-28
申请人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Andrew C. Singer , Jonathan B. Ashbrook
发明人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Andrew C. Singer , Jonathan B. Ashbrook
IPC分类号： G01R13/02
CPC分类号： H03D13/00 , H03L7/091
摘要： Methods and systems are provided for an improved phase detector utilizing analog-to-digital converter (ADC) components. In an embodiment, the method includes from an ADC having a sampling clock signal that determines sampling instants, obtaining a first comparison value between an analog signal and a first threshold voltage at a first sampling instant, and obtaining a second comparison value between the analog signal and a second threshold voltage at a second sampling instant. The method further includes, from a supplemental circuit, obtaining a third comparison value between the analog signal and a third threshold voltage at a third sampling instant between the first and second sampling instants. The method further includes processing the first, second, and third comparison values to determine a phase relationship between the analog signal and the sampling clock.
摘要翻译：为使用模数转换器（ADC）组件的改进的相位检测器提供了方法和系统。在一个实施例中，该方法包括来自具有确定采样时刻的采样时钟信号的ADC，在第一采样时刻获得模拟信号和第一阈值电压之间的第一比较值，以及获得模拟信号之间的第二比较值和第二采样时刻的第二阈值电压。该方法还包括从补充电路在第一和第二采样时刻之间的第三采样时刻获得模拟信号和第三阈值电压之间的第三比较值。该方法还包括处理第一，第二和第三比较值以确定模拟信号和采样时钟之间的相位关系。

6. 发明申请

US20090072903A1 Variable Gain Amplifier Having Variable Gain DC Offset Loop 有权
标题翻译：具有可变增益直流偏移环路的可变增益放大器
公开(公告)号：US20090072903A1
公开(公告)日：2009-03-19
申请号：US11856680
申请日：2007-09-17
申请人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Jonathan B. Ashbrook
发明人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Jonathan B. Ashbrook
IPC分类号： H03F3/45
CPC分类号： H03F3/45098 , H03F3/45085 , H03F3/45179 , H03F3/45475 , H03F3/45968 , H03F2203/45138 , H03F2203/45506 , H03F2203/45521 , H03F2203/45722 , H03F2203/45728
摘要： A variable gain amplifier and offset cancellation loop circuit and methods for tracking and correcting DC offset errors that may vary in accordance with the gain of the variable gain amplifier. The circuit is designed to provide tracking of rapid changes in the offset error while maintaining a desired overall frequency response of the combined variable gain amplifier and offset loop. The offset loop cancellation circuit has a wide enough bandwidth to allow the offset cancellation loop to track rapid changes in offset errors that result from rapid changes to the amplifier's gain setting. A control circuit is provided to prevent the large offset cancellation loop bandwidth from having a detrimental effect on the amplifier's overall bandwidth when the amplifier is set to high levels of forward gain by adjusting the offset cancellation loop gain as the forward gain of the amplifier is altered.
摘要翻译：可变增益放大器和偏移消除环路电路以及跟踪和校正可能根据可变增益放大器的增益而变化的直流偏移误差的方法。该电路被设计为提供对偏移误差的快速变化的跟踪，同时保持组合的可变增益放大器和偏移环路的期望的总体频率响应。偏移回路消除电路具有足够宽的带宽，以允许偏移消除环路跟踪由放大器的增益设置的快速变化导致的偏移误差的快速变化。提供控制电路以防止大的偏移消除环路带宽对放大器的整体带宽产生不利影响，当放大器被设置为高电平的正向增益时，通过调整偏移消除环路增益，因为放大器的正向增益被改变。

7. 发明申请

US20090072865A1 Peak Detector with Active Ripple Suppression 有权
标题翻译：峰值检测器，有效波纹抑制
公开(公告)号：US20090072865A1
公开(公告)日：2009-03-19
申请号：US11856691
申请日：2007-09-17
申请人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Jonathan B. Ashbrook
发明人： Hyeon Min Bae , Naresh Ramnath Shanbhag , Jonathan B. Ashbrook
IPC分类号： H03K5/1532
CPC分类号： H03K5/1532
摘要： A peak detector circuit that responds rapidly to power transients, and yet is able to avoid interpreting data fluctuations as power transients by generating dual peak signals from an amplifier's differential output signal, where the dual peak signals have data ripple components that tend to cancel one another. The system and methods permit the peak detectors to be much more responsive to power transients by expanding their bandwith (shortening the time constants) to the point that low frequency data components affect the individual peak detector signals, but the effects are cancelled out when the individual components are added together. The peak detector described herein may be used in an AGC system to provide ripple-free gain control signals, while rapidly following any power transients in transmitted signals.
摘要翻译：峰值检测器电路可以快速响应功率瞬变，并且能够通过从放大器的差分输出信号产生双峰值信号来避免将数据波动解释为功率瞬变，其中双峰值信号具有倾向于彼此抵消的数据波动分量。该系统和方法允许峰值检测器通过将其带宽（缩短时间常数）扩展到低频数据分量影响各个峰值检测器信号的点而对功率瞬态响应更大，但是当个体组件添加在一起。本文描述的峰值检测器可用于AGC系统中，以在快速跟随发射信号中的任何功率瞬变之后提供无纹波增益控制信号。

8. 发明授权

US07609102B2 Pattern-dependent phase detector for clock recovery 有权
标题翻译：用于时钟恢复的模式相关相位检测器
公开(公告)号：US07609102B2
公开(公告)日：2009-10-27
申请号：US11420196
申请日：2006-05-24
申请人： Naresh Shanbhag , Hyeon Min Bae , Jinki Park , Paul Suppiah
发明人： Naresh Shanbhag , Hyeon Min Bae , Jinki Park , Paul Suppiah
IPC分类号： H03H11/16
CPC分类号： H03D13/003 , H03L7/091 , H04L7/033
摘要： A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.
摘要翻译：提供了一种用于从数据信号进行时钟恢复的相位检测器装置和方法。相位检测器向时钟信号发生器提供相位校正信号，其中仅在观察到预定的数据样本图样时才产生相位校正信号。特别地，预定的数据样本图案优选地是从1到0的转变。因此，即使发生了转换，从零转换到一个也不会提供有效的相位更新输出信号。在其他实施例中，预定数据样本模式优选地是在附加逻辑1个样本之前的一到零转换。

9. 发明授权

US07298226B2 Noise tolerant voltage controlled oscillator 有权
标题翻译：耐噪声压控振荡器
公开(公告)号：US07298226B2
公开(公告)日：2007-11-20
申请号：US11420195
申请日：2006-05-24
申请人： Naresh Shanbhag , Hyeon Min Bae , Jinki Park , Paul Suppiah
发明人： Naresh Shanbhag , Hyeon Min Bae , Jinki Park , Paul Suppiah
IPC分类号： H03B1/00
CPC分类号： H03D13/003 , H03L7/091 , H04L7/033
摘要： A noise tolerant voltage controlled oscillator is described. The voltage controlled oscillator include a varactor element as part of an LC tank circuit. The varactor element is biased by a bias signal and a bias-dependent control signal. The bias-dependent control signal tunes the LC tank circuit. Because the control signal is bias-dependent, noise and other deleterious influences do not cause the varactor element to deviate in capacitance. Instead, the bias-dependent control signal is a tuning signal that is centered around the bias signal, which allows the varactor element to provide a constant capacitance in the event of a varying bias signal.
摘要翻译：描述了一种耐噪声压控振荡器。压控振荡器包括作为LC谐振电路的一部分的变容二极管元件。变容二极管元件被偏置信号和偏置依赖控制信号偏置。偏置相关的控制信号调节LC电路。因为控制信号是偏置相关的，所以噪声和其他有害影响不会导致变容二极管元件偏离电容。相反，偏置依赖控制信号是以偏置信号为中心的调谐信号，其允许变容二极管元件在变化的偏置信号的情况下提供恒定的电容。

10. 发明申请

US20090237138A1 PATTERN-DEPENDENT PHASE DETECTOR FOR CLOCK RECOVERY 有权
标题翻译：用于时钟恢复的图案相关检测器
公开(公告)号：US20090237138A1
公开(公告)日：2009-09-24
申请号：US11420196
申请日：2006-05-24
申请人： Naresh Shanbhag , Hyeon Min Bae , Jinki Park , Paul Suppiah
发明人： Naresh Shanbhag , Hyeon Min Bae , Jinki Park , Paul Suppiah
IPC分类号： H03H11/16
CPC分类号： H03D13/003 , H03L7/091 , H04L7/033
摘要： A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.
摘要翻译：提供了一种用于从数据信号进行时钟恢复的相位检测器装置和方法。相位检测器向时钟信号发生器提供相位校正信号，其中仅在观察到预定的数据样本图样时才产生相位校正信号。特别地，预定的数据样本图案优选地是从1到0的转变。因此，即使发生了转换，从零转换到一个也不会提供有效的相位更新输出信号。在其他实施例中，预定数据样本模式优选地是在附加逻辑1个样本之前的一到零转换。

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