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1. 发明申请

US20100090348A1 Single-Sided Trench Contact Window 审中-公开
标题翻译：单面沟槽接触窗口
公开(公告)号：US20100090348A1
公开(公告)日：2010-04-15
申请号：US12249104
申请日：2008-10-10
申请人： Inho Park , Hans-Peter Moll , Gouri Sankar Kar , Lars Heineck
发明人： Inho Park , Hans-Peter Moll , Gouri Sankar Kar , Lars Heineck
IPC分类号： H01L23/48 , H01L21/76 , H01L21/82
CPC分类号： H01L21/743
摘要： An integrated circuit is manufactured from a semiconductor substrate having trenches with first and second sidewalls facing each other and a conductive line arranged in a bottom region of the trenches. At least the bottom region of the trenches is lined with an insulative material between the conductive line and the substrate. A first sacrificial layer is formed above the conductive line adjacent the first and second sidewalls. The trenches are filled with one or more additional sacrificial layers having a different etch selectivity than the first sacrificial layer. A portion of the one or more additional sacrificial layers and a portion of the insulative material are selectively removed to the first sacrificial layer so that the substrate is exposed below the first sacrificial layer along the first trench sidewalls and covered by the insulative material along the second trench sidewalls.
摘要翻译：集成电路由具有第一和第二侧壁彼此面对的沟槽的半导体衬底和布置在沟槽的底部区域中的导电线制成。沟槽的至少底部区域在导电线和衬底之间衬有绝缘材料。第一牺牲层形成在与第一和第二侧壁相邻的导电线的上方。沟槽填充有一个或多个具有与第一牺牲层不同的蚀刻选择性的附加牺牲层。所述一个或多个附加牺牲层的一部分和所述绝缘材料的一部分被选择性地移除到所述第一牺牲层，使得所述衬底沿着所述第一沟槽侧壁暴露在所述第一牺牲层下方并且沿着所述第二牺牲层被所述绝缘材料覆盖沟槽侧壁。

2. 发明授权

US08138538B2 Interconnect structure for semiconductor devices 有权
标题翻译：半导体器件的互连结构
公开(公告)号：US08138538B2
公开(公告)日：2012-03-20
申请号：US12249060
申请日：2008-10-10
申请人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
发明人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
IPC分类号： H01L27/108
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。互连件包括布置在半导体本体表面下方的金属体。接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。还公开了其它方法，装置和系统。

3. 发明申请

US20100090264A1 INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件的互连结构
公开(公告)号：US20100090264A1
公开(公告)日：2010-04-15
申请号：US12249060
申请日：2008-10-10
申请人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
发明人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。互连件包括布置在半导体本体表面下方的金属体。接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。还公开了其它方法，装置和系统。

4. 发明授权

US06916721B2 Method for fabricating a trench capacitor with an insulation collar 失效
标题翻译：用于制造具有绝缘套圈的沟槽电容器的方法
公开(公告)号：US06916721B2
公开(公告)日：2005-07-12
申请号：US10722360
申请日：2003-11-26
申请人： Lars Heineck , Stephan Kudelka , Jörn Lützen , Hans-Peter Moll , Martin Popp , Till Schlösser , Johann Steinmetz
发明人： Lars Heineck , Stephan Kudelka , Jörn Lützen , Hans-Peter Moll , Martin Popp , Till Schlösser , Johann Steinmetz
IPC分类号： H01L21/20 , H01L21/334 , H01L21/425 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10867 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.
摘要翻译：一种在衬底中制造具有绝缘套环的沟槽电容器的方法，其使用具有相应掩模开口的硬掩模经由掩埋触点将其一侧的衬底电连接。

5. 发明申请

US20140159140A1 BURIED WORD LINE STRUCTURE AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20140159140A1
公开(公告)日：2014-06-12
申请号：US13706366
申请日：2012-12-06
申请人： Inho Park , Lars Heineck
发明人： Inho Park , Lars Heineck
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/76224 , H01L21/28017 , H01L27/115 , H01L29/7827
摘要： A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.
摘要翻译：提供一种形成掩埋字线结构的方法。第一掩模层，中间层和第二掩模层依次形成在基板上，其中第二掩模层具有多个掩模图案和交替布置的多个间隙，并且间隙包括交替布置的第一间隙和第二间隙。在每个第一间隙中形成电介质图案，并且间隔件同时形成在每个第二间隙的侧壁上，其中在相邻间隔物之间形成第一沟槽并露出第一掩模层的一部分。去除掩模图案以形成第二沟槽。通过使用电介质图案和间隔物作为掩模来执行蚀刻工艺，使得第一沟槽加深到衬底，并且第二沟槽加深到第一掩模层。

6. 发明授权

US08735267B1 Buried word line structure and method of forming the same 有权
标题翻译：掩埋字线结构及其形成方法
公开(公告)号：US08735267B1
公开(公告)日：2014-05-27
申请号：US13706366
申请日：2012-12-06
申请人： Inho Park , Lars Heineck
发明人： Inho Park , Lars Heineck
IPC分类号： H01L21/20
CPC分类号： H01L21/76224 , H01L21/28017 , H01L27/115 , H01L29/7827
摘要： A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.
摘要翻译：提供一种形成掩埋字线结构的方法。第一掩模层，中间层和第二掩模层依次形成在基板上，其中第二掩模层具有多个掩模图案和交替布置的多个间隙，并且间隙包括交替布置的第一间隙和第二间隙。在每个第一间隙中形成电介质图案，并且间隔件同时形成在每个第二间隙的侧壁上，其中在相邻间隔物之间形成第一沟槽并露出第一掩模层的一部分。去除掩模图案以形成第二沟槽。通过使用电介质图案和间隔物作为掩模来执行蚀刻工艺，使得第一沟槽加深到衬底，并且第二沟槽加深到第一掩模层。

7. 发明申请

US20120329274A1 METHOD OF FABRICATING A CELL CONTACT AND A DIGIT LINE FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：细胞接触方法和半导体器件的数字线
公开(公告)号：US20120329274A1
公开(公告)日：2012-12-27
申请号：US13164778
申请日：2011-06-21
申请人： Shyam Surthi , Lars Heineck
发明人： Shyam Surthi , Lars Heineck
IPC分类号： H01L21/28
CPC分类号： H01L27/10855 , H01L27/10885
摘要： The present invention proposes the use of a silicon nitride layer on top of a second conductive layer. After a step of etching a second conductive layer, an oxide spacer is formed to define a gap. Then, another silicon nitride layer fills up the gap. After that, the oxide spacer is removed. Later, a first conductive layer is etched to separate the digit line to cell contact line.
摘要翻译：本发明提出了在第二导电层的顶部上使用氮化硅层。在蚀刻第二导电层的步骤之后，形成氧化物间隔物以限定间隙。然后，另一个氮化硅层填满间隙。之后，除去氧化物间隔物。之后，蚀刻第一导电层以将数字线分隔成细胞接触线。

8. 发明申请

US20080299722A1 Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure 审中-公开
标题翻译：用于形成凹陷沟道晶体管的制造方法，用于形成相应的集成半导体存储器件的方法和相应的自对准掩模结构
公开(公告)号：US20080299722A1
公开(公告)日：2008-12-04
申请号：US11807550
申请日：2007-05-29
申请人： Jessica Hartwich , Andrew Graham , Arnd Scholz , Yimin Wang , Stefan Slesazeck , Lars Heineck , Franz Hofmann
发明人： Jessica Hartwich , Andrew Graham , Arnd Scholz , Yimin Wang , Stefan Slesazeck , Lars Heineck , Franz Hofmann
IPC分类号： H01L21/8242
CPC分类号： H01L29/66621 , H01L27/10876 , H01L29/4236 , H01L29/945
摘要： The present invention provides a method for forming a recessed channel transistor comprising the steps of: forming a plurality of active areas lines in a semiconductor substrate with an upper surface, said lines being segmented by segmentation structures having an upper surface height differing from the substrate surface; forming a first and a second extension region arranged above the active area and adjacent said segmentation structures; forming recessed channel devices in the active area segments in the remaining portion of the active area segment between said extension regions.
摘要翻译：本发明提供了一种用于形成凹陷沟道晶体管的方法，包括以下步骤：在具有上表面的半导体衬底中形成多个有源区线，所述线被具有不同于衬底表面的上表面高度的分割结构分割 ; 形成布置在所述有效区域上方并邻近所述分割结构的第一和第二延伸区域; 在所述延伸区域之间的有源区段的剩余部分中的有源区段中形成凹陷通道器件。

9. 发明申请

US20070290249A1 Integrated Circuit Including a Memory Cell Array 审中-公开
标题翻译：包含存储单元阵列的集成电路
公开(公告)号：US20070290249A1
公开(公告)日：2007-12-20
申请号：US11844853
申请日：2007-08-24
申请人： Martin Popp , Frank Jakubowski , Juergen Holz , Lars Heineck
发明人： Martin Popp , Frank Jakubowski , Juergen Holz , Lars Heineck
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L21/26586 , H01L27/0207 , H01L27/10823 , H01L27/10829 , H01L27/10873 , H01L27/10885 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit includes a memory cell array comprising memory cells with a transistor. The transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed under the bottom side of each word line. In addition, the word lines are disposed over the bit lines.
摘要翻译：集成电路包括具有晶体管的存储单元的存储单元阵列。晶体管形成在有源区域中。存储单元阵列还包括沿第一方向定向的位线和朝向第二方向的字线。有源区域沿第二方向延伸。晶体管的每个栅电极的底侧设置在每个字线的底侧的下方。此外，字线设置在位线之上。

10. 发明授权

US09337201B2 Memory cells, arrays of memory cells, and methods of forming memory cells 有权
公开(公告)号：US09337201B2
公开(公告)日：2016-05-10
申请号：US13612507
申请日：2012-09-12
申请人： Lars Heineck , Jaydip Guha
发明人： Lars Heineck , Jaydip Guha
IPC分类号： H01L27/088 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10882 , H01L27/10885 , H01L27/10888
摘要： A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed.

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