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1. 发明申请

US20170040981A1 SEQUENCED PULSE-WIDTH ADJUSTMENT IN A RESONANT CLOCKING CIRCUIT 有权
标题翻译：谐振时钟电路中的顺序脉冲宽度调整
公开(公告)号：US20170040981A1
公开(公告)日：2017-02-09
申请号：US14828841
申请日：2015-08-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Phillip J. Restle , David Wen-Hao Shan
IPC分类号： H03K3/012 , G06F1/10 , H03K9/08
CPC分类号： H03K3/012 , G06F1/08 , G06F1/10 , H03K5/06 , H03K7/08 , H03K9/08
摘要： A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
摘要翻译：用于谐振时钟分配网络的时钟驱动器控制方案通过控制驱动谐振时钟分配网络的时钟驱动器电路的输出的脉冲宽度来提供鲁棒的操作，使得改变被排序。时钟驱动器控制电路通过提供给对应的时钟驱动器电路的多个控制信号，根据所选择的操作模式控制相应扇区中的时钟驱动器电路。在具有耦合到谐振时钟分配网络的时钟输入的集成电路内的数字电路的操作期间，至少一些扇区的脉冲宽度不同。不同的脉冲宽度可以是响应于向时钟驱动器电路提供输入的全局时钟的模式或频率变化而施加的瞬态差异。

2. 发明授权

US08850373B2 Setting switch size and transition pattern in a resonant clock distribution system 有权
公开(公告)号：US08850373B2
公开(公告)日：2014-09-30
申请号：US14136770
申请日：2013-12-20
申请人： International Business Machines Corporation
发明人： Jason D. Hibbeler , William R. Reohr , Phillip J. Restle
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5045 , G06F17/5068 , G06F2217/62 , G06F2217/78 , H03K5/00 , H03K2005/00195
摘要： Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.

3. 发明申请

US20140218087A1 Wide Bandwidth Resonant Global Clock Distribution 有权
标题翻译：宽带宽共振全局时钟分配
公开(公告)号：US20140218087A1
公开(公告)日：2014-08-07
申请号：US13759311
申请日：2013-02-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G.R. Thomson
IPC分类号： H03K5/06
CPC分类号： H03K5/06 , G06F1/10
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
摘要翻译：宽带谐振时钟分配包括被配置为将时钟信号分配给集成电路的多个分量的时钟网格，配置成接收时钟信号并向时钟网格提供输出的可调谐扇区缓冲器，至少一个电感器，至少一个可调谐电阻开关和电容器网络。可调谐扇区缓冲器可编程设置时钟信号的延时和转换速率。电感，可调电阻开关和电容网络连接在时钟网格和参考电压之间。所述至少一个可调谐电阻开关是可编程的，以基于所述时钟信号的频率，将所述至少一个电感器动态地切换到所述时钟分布中或者从所述时钟分布中产生至少一个谐振模式或非谐振模式。

4. 发明申请

US20140201561A1 CLOCK SKEW ANALYSIS AND OPTIMIZATION 有权
标题翻译：时钟分析和优化
公开(公告)号：US20140201561A1
公开(公告)日：2014-07-17
申请号：US13742039
申请日：2013-01-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Phillip J. Restle , James D. Warnock
IPC分类号： G06F1/10
CPC分类号： G06F1/10 , G06F17/5031
摘要： A method for adjusting clock skew in a network is disclosed. A model is fit to a first clock input signal received at a first receiver of the network and to a second clock input signal received at a second receiver of the network to obtain a fitted model. A first response signal is simulated using the fitted model and the first clock input signal and a second response signal is simulated using the fitted model and the second clock input signal. A time difference is determined between the simulated first response signal and the simulated second response signal. A parameter of at least one of the network clock network, the first receiver and the second receiver is altered to adjust the determined time difference.
摘要翻译：公开了一种用于调整网络中的时钟偏移的方法。模型适合于在网络的第一接收机处接收的第一时钟输入信号和适合在网络的第二接收机处接收的第二时钟输入信号以获得拟合模型。使用拟合模型和第一时钟输入信号来模拟第一响应信号，并且使用拟合模型和第二时钟输入信号来模拟第二响应信号。在模拟的第一响应信号和模拟的第二响应信号之间确定时间差。改变网络时钟网络，第一接收机和第二接收机中的至少一个的参数以调整确定的时间差。

5. 发明授权

US09634654B2 Sequenced pulse-width adjustment in a resonant clocking circuit 有权
公开(公告)号：US09634654B2
公开(公告)日：2017-04-25
申请号：US14820726
申请日：2015-08-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Phillip J. Restle , David Wen-Hao Shan
IPC分类号： G06F1/10 , H03K3/00 , H03K7/08
CPC分类号： H03K3/012 , G06F1/08 , G06F1/10 , H03K5/06 , H03K7/08 , H03K9/08
摘要： A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

6. 发明授权

US09612612B2 Tunable sector buffer for wide bandwidth resonant global clock distribution 有权
公开(公告)号：US09612612B2
公开(公告)日：2017-04-04
申请号：US14706166
申请日：2015-05-07
申请人： International Business Machines Corporation
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G. R. Thomson
IPC分类号： H03K3/00 , G06F1/10 , G06F1/04
CPC分类号： G06F1/10 , G06F1/324 , Y02D10/126
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.

7. 发明授权

US09268886B2 Setting switch size and transition pattern in a resonant clock distribution system 有权
标题翻译：在谐振时钟分配系统中设置开关尺寸和转换模式
公开(公告)号：US09268886B2
公开(公告)日：2016-02-23
申请号：US14136651
申请日：2013-12-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jason D. Hibbeler , William R. Reohr , Phillip J. Restle
IPC分类号： G06F17/50 , H03K5/00
CPC分类号： G06F17/5009 , G06F17/5045 , G06F17/5068 , G06F2217/62 , G06F2217/78 , H03K5/00 , H03K2005/00195
摘要： Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.
摘要翻译：提供了时钟分配网络中的回收能量。一种方法包括创建包括时钟网格的谐振时钟电路。该方法还包括提供分布在时钟网格中的谐振结构。该方法还包括提供控制谐振结构以在非谐振模式和谐振模式之间切换的开关。该方法还包括确定通过迭代地增加开关的尺寸来最小化谐振时钟电路的功耗的开关尺寸，并且对于每个迭代增加的尺寸，确定谐振时钟电路消耗的功率。

8. 发明授权

US09231603B2 Distributed phase detection for clock synchronization in multi-layer 3D stacks 有权
标题翻译：分层相位检测用于多层3D堆叠中的时钟同步
公开(公告)号：US09231603B2
公开(公告)日：2016-01-05
申请号：US14230859
申请日：2014-03-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Yong Liu , Liang-Teck Pang , Phillip J. Restle
IPC分类号： H03K5/01 , H03L7/087
CPC分类号： H03L7/087 , G06F1/12 , H03L7/0812
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution circuit includes, on each of the two or more strata, phase detectors, a logic circuit, and a phase de-skewing element. Each phase detector has a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata. The logic circuit is connected to the respective outputs of the phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information. The phase de-skewing element is for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan.
摘要翻译：提供了一种时钟分配网络，用于在具有两个或更多个层的3D芯片堆栈内同步全局时钟信号。时钟分配电路在两个或更多个层中的每一个上包括相位检测器，逻辑电路和相位偏移元件。每个相位检测器具有相应的输出，用于提供与两个或更多个层的各个不同层上的两个全局时钟信号之间的相位差有关的相位信息。逻辑电路连接到相位检测器的相应输出端，用于确定逻辑电路响应于相位信息所位于的两个或更多个层中给定的一个给定的一个的相位调整计划。相位去偏移元件用于响应于相位调整方案来调整位于两个全球时钟信号之一的同一层的时钟偏移。

9. 发明授权

US09054682B2 Wide bandwidth resonant global clock distribution 有权
标题翻译：宽带宽谐振全局时钟分布
公开(公告)号：US09054682B2
公开(公告)日：2015-06-09
申请号：US13759311
申请日：2013-02-05
申请人： International Business Machines Corporation
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G. R. Thomson
IPC分类号： G06F1/10 , H03K5/06
CPC分类号： H03K5/06 , G06F1/10
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
摘要翻译：宽带谐振时钟分配包括被配置为将时钟信号分配给集成电路的多个分量的时钟网格，配置成接收时钟信号并向时钟网格提供输出的可调谐扇区缓冲器，至少一个电感器，至少一个可调谐电阻开关和电容器网络。可调谐扇区缓冲器可编程设置时钟信号的延时和转换速率。电感，可调电阻开关和电容网络连接在时钟网格和参考电压之间。所述至少一个可调谐电阻开关是可编程的，以基于所述时钟信号的频率，将所述至少一个电感器动态地切换到所述时钟分布中或者从所述时钟分布中产生至少一个谐振模式或非谐振模式。

10. 发明授权

US08704576B1 Variable resistance switch for wide bandwidth resonant global clock distribution 有权
标题翻译：用于宽带宽谐振全局时钟分配的可变电阻开关
公开(公告)号：US08704576B1
公开(公告)日：2014-04-22
申请号：US13759697
申请日：2013-02-05
申请人： International Business Machines Corporation
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G. R. Thomson
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, at least one inductor, at least one tunable resistance switch, and a capacitor network. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
摘要翻译：宽带谐振时钟分布包括被配置为将时钟信号分配到集成电路的多个部件，至少一个电感器，至少一个可调电阻开关和电容器网络的时钟网格。电感，可调电阻开关和电容网络连接在时钟网格和参考电压之间。所述至少一个可调谐电阻开关是可编程的，以基于所述时钟信号的频率，将所述至少一个电感器动态地切换到所述时钟分布中或者从所述时钟分布中产生至少一个谐振模式或非谐振模式。

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