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1. 发明申请

US20170040981A1 SEQUENCED PULSE-WIDTH ADJUSTMENT IN A RESONANT CLOCKING CIRCUIT 有权
标题翻译：谐振时钟电路中的顺序脉冲宽度调整
公开(公告)号：US20170040981A1
公开(公告)日：2017-02-09
申请号：US14828841
申请日：2015-08-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Phillip J. Restle , David Wen-Hao Shan
IPC分类号： H03K3/012 , G06F1/10 , H03K9/08
CPC分类号： H03K3/012 , G06F1/08 , G06F1/10 , H03K5/06 , H03K7/08 , H03K9/08
摘要： A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
摘要翻译：用于谐振时钟分配网络的时钟驱动器控制方案通过控制驱动谐振时钟分配网络的时钟驱动器电路的输出的脉冲宽度来提供鲁棒的操作，使得改变被排序。时钟驱动器控制电路通过提供给对应的时钟驱动器电路的多个控制信号，根据所选择的操作模式控制相应扇区中的时钟驱动器电路。在具有耦合到谐振时钟分配网络的时钟输入的集成电路内的数字电路的操作期间，至少一些扇区的脉冲宽度不同。不同的脉冲宽度可以是响应于向时钟驱动器电路提供输入的全局时钟的模式或频率变化而施加的瞬态差异。

2. 发明申请

US20140218087A1 Wide Bandwidth Resonant Global Clock Distribution 有权
标题翻译：宽带宽共振全局时钟分配
公开(公告)号：US20140218087A1
公开(公告)日：2014-08-07
申请号：US13759311
申请日：2013-02-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G.R. Thomson
IPC分类号： H03K5/06
CPC分类号： H03K5/06 , G06F1/10
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
摘要翻译：宽带谐振时钟分配包括被配置为将时钟信号分配给集成电路的多个分量的时钟网格，配置成接收时钟信号并向时钟网格提供输出的可调谐扇区缓冲器，至少一个电感器，至少一个可调谐电阻开关和电容器网络。可调谐扇区缓冲器可编程设置时钟信号的延时和转换速率。电感，可调电阻开关和电容网络连接在时钟网格和参考电压之间。所述至少一个可调谐电阻开关是可编程的，以基于所述时钟信号的频率，将所述至少一个电感器动态地切换到所述时钟分布中或者从所述时钟分布中产生至少一个谐振模式或非谐振模式。

3. 发明授权

US10141915B2 Sequenced pulse-width adjustment in a resonant clocking circuit 有权
公开(公告)号：US10141915B2
公开(公告)日：2018-11-27
申请号：US15479420
申请日：2017-04-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Phillip J. Restle , David Wen-Hao Shan
IPC分类号： G05F1/04 , H03K3/00 , H03K3/012 , H03K7/08 , G06F1/10 , H03K9/08 , H03K5/06 , G06F1/08
摘要： A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

4. 发明授权

US09618966B2 Pulse-drive resonant clock with on-the-fly mode change 有权
公开(公告)号：US09618966B2
公开(公告)日：2017-04-11
申请号：US14828898
申请日：2015-08-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Robert L. Franch , Phillip J. Restle , David Wen-Hao Shan , Christos Vezyrtzis
IPC分类号： H03K7/08 , G06F1/10 , H03K5/159
CPC分类号： G06F1/10 , G06F1/324 , H03K5/159 , H03K7/08 , Y02D10/126
摘要： A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.

5. 发明授权

US08736342B1 Changing resonant clock modes 有权
标题翻译：改变谐振时钟模式
公开(公告)号：US08736342B1
公开(公告)日：2014-05-27
申请号：US13719408
申请日：2012-12-19
申请人： International Business Machines Corporation
发明人： Thomas J. Bucelot , Alan Drake , Joshua D. Friedrich , Jason D. Hibbeler , Liang-Teck Pang , William R. Reohr , Phillip John Restle , Gregory S. Still , Michael G. R. Thomson
IPC分类号： G06F1/10
CPC分类号： G06F1/10
摘要： Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.
摘要翻译：描述了具有能够从非共振时钟模式转换到第一谐振时钟模式的时钟分配网络的集成电路。在一系列时钟周期内，逐渐完成在时钟模式之间或各种谐振时钟频率之间的转换。例如，当从非共振时钟模式转换到第一谐振时钟模式时，时钟扇区驱动器的强度在一系列时钟周期内减小，并且与谐振电路相关联的多个谐振开关中的各个谐振开关被修改协调减少时钟扇区驱动程序的实力。

6. 发明授权

US09634654B2 Sequenced pulse-width adjustment in a resonant clocking circuit 有权
公开(公告)号：US09634654B2
公开(公告)日：2017-04-25
申请号：US14820726
申请日：2015-08-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Phillip J. Restle , David Wen-Hao Shan
IPC分类号： G06F1/10 , H03K3/00 , H03K7/08
CPC分类号： H03K3/012 , G06F1/08 , G06F1/10 , H03K5/06 , H03K7/08 , H03K9/08
摘要： A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

7. 发明授权

US09612612B2 Tunable sector buffer for wide bandwidth resonant global clock distribution 有权
公开(公告)号：US09612612B2
公开(公告)日：2017-04-04
申请号：US14706166
申请日：2015-05-07
申请人： International Business Machines Corporation
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G. R. Thomson
IPC分类号： H03K3/00 , G06F1/10 , G06F1/04
CPC分类号： G06F1/10 , G06F1/324 , Y02D10/126
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.

8. 发明授权

US09054682B2 Wide bandwidth resonant global clock distribution 有权
标题翻译：宽带宽谐振全局时钟分布
公开(公告)号：US09054682B2
公开(公告)日：2015-06-09
申请号：US13759311
申请日：2013-02-05
申请人： International Business Machines Corporation
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G. R. Thomson
IPC分类号： G06F1/10 , H03K5/06
CPC分类号： H03K5/06 , G06F1/10
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
摘要翻译：宽带谐振时钟分配包括被配置为将时钟信号分配给集成电路的多个分量的时钟网格，配置成接收时钟信号并向时钟网格提供输出的可调谐扇区缓冲器，至少一个电感器，至少一个可调谐电阻开关和电容器网络。可调谐扇区缓冲器可编程设置时钟信号的延时和转换速率。电感，可调电阻开关和电容网络连接在时钟网格和参考电压之间。所述至少一个可调谐电阻开关是可编程的，以基于所述时钟信号的频率，将所述至少一个电感器动态地切换到所述时钟分布中或者从所述时钟分布中产生至少一个谐振模式或非谐振模式。

9. 发明授权

US08704576B1 Variable resistance switch for wide bandwidth resonant global clock distribution 有权
标题翻译：用于宽带宽谐振全局时钟分配的可变电阻开关
公开(公告)号：US08704576B1
公开(公告)日：2014-04-22
申请号：US13759697
申请日：2013-02-05
申请人： International Business Machines Corporation
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G. R. Thomson
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, at least one inductor, at least one tunable resistance switch, and a capacitor network. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.
摘要翻译：宽带谐振时钟分布包括被配置为将时钟信号分配到集成电路的多个部件，至少一个电感器，至少一个可调电阻开关和电容器网络的时钟网格。电感，可调电阻开关和电容网络连接在时钟网格和参考电压之间。所述至少一个可调谐电阻开关是可编程的，以基于所述时钟信号的频率，将所述至少一个电感器动态地切换到所述时钟分布中或者从所述时钟分布中产生至少一个谐振模式或非谐振模式。

10. 发明申请

US20170207772A1 SEQUENCED PULSE-WIDTH ADJUSTMENT IN A RESONANT CLOCKING CIRCUIT 审中-公开
公开(公告)号：US20170207772A1
公开(公告)日：2017-07-20
申请号：US15479420
申请日：2017-04-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Phillip J. Restle , David Wen-Hao Shan
IPC分类号： H03K3/012 , G06F1/08 , H03K7/08
CPC分类号： H03K3/012 , G06F1/08 , G06F1/10 , H03K5/06 , H03K7/08 , H03K9/08
摘要： A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

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