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1. 发明授权

US5213916A Method of making a gray level mask 失效
标题翻译：制作灰度掩码的方法
公开(公告)号：US5213916A
公开(公告)日：1993-05-25
申请号：US605606
申请日：1990-10-30
申请人： John E. Cronin , Paul A. Farrar, Sr. , Carter W. Kaanta , James G. Ryan , Andrew J. Watts
发明人： John E. Cronin , Paul A. Farrar, Sr. , Carter W. Kaanta , James G. Ryan , Andrew J. Watts
IPC分类号： G03F1/00 , G03F7/00 , G03F9/00 , H01L21/027
CPC分类号： G03F7/0035 , G03F1/50
摘要： A gray level mask suitable for photolithography is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. The mask is fabricated with the aid of a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist, the metal of one of the layers, and the glass of the other of the layers. The etches include plasma etch with chloride ions to attack the chromium of the opaque layer, compounds of fluorine to attack the glass layer, and reactive ion etching with oxygen to attack the photoresist structure. Also, developer is employed for etching on hardened regions of resist in the photoresist structure.
摘要翻译：适用于光刻的灰度级掩模由透明玻璃基板构成，该透明玻璃基板支持具有不同透光率的多层材料。在仅使用这些水平中的两个的掩模的情况下，一个层可以由通过取代银离子代替在玻璃的结构中使用的碱金属硅酸盐的金属离子而部分透射的玻璃构成。第二层可以通过金属如铬的构造而变得不透明。借助于光致抗蚀剂结构制造掩模，该光致抗蚀剂结构通过光刻掩模在特定区域中被蚀刻，以使得能够选择性地蚀刻具有不同光学透射率的材料层的暴露区域。各种蚀刻用于选择性蚀刻光致抗蚀剂，其中一层的金属和另一层的玻璃。蚀刻包括用氯离子等离子体蚀刻以侵蚀不透明层的铬，氟的化合物侵蚀玻璃层，以及用氧反应离子蚀刻以侵蚀光致抗蚀剂结构。此外，显影剂用于蚀刻光致抗蚀剂结构中的抗蚀剂的硬化区域。

2. 发明授权

US4789648A Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias 失效
标题翻译：在基板上制造共面多层金属/绝缘体膜并与螺柱通孔同时形成图案化导电线的方法
公开(公告)号：US4789648A
公开(公告)日：1988-12-06
申请号：US791887
申请日：1985-10-28
申请人： Melanie M. Chow , John E. Cronin , William L. Guthrie , Carter W. Kaanta , Barbara Luther , William J. Patrick , Kathleen A. Perry , Charles L. Standley
发明人： Melanie M. Chow , John E. Cronin , William L. Guthrie , Carter W. Kaanta , Barbara Luther , William J. Patrick , Kathleen A. Perry , Charles L. Standley
IPC分类号： H01L21/3205 , H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/3213 , H01L21/768 , H05K3/04 , H05K3/10 , H05K3/46 , H01L21/306
CPC分类号： H01L21/7681 , H01L21/304 , H01L21/32134 , H01L21/7684 , H01L21/76877 , H05K3/04 , H05K3/107 , H05K3/4644
摘要： Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time.Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material.The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.
摘要翻译：图案化的导线通过连接通过绝缘层与螺柱同时形成，以预先形成的多层VLSI芯片技术中的下面的图案化导电线。第一平坦化绝缘层沉积在要选择性地建立触点的图案化导电材料的第一层上。第一层然后被蚀刻停止材料覆盖。在需要螺柱连接器的位置处，在蚀刻停止材料中限定接触孔。此时第一层绝缘层不被蚀刻。接下来，将第二平坦化绝缘层沉积在蚀刻停止材料上。再次通过光刻将第二层绝缘层蚀刻到蚀刻停止材料上，以限定所需的布线通道，其中的一些布线通道将与蚀刻停止材料中先前形成的接触孔对准。在暴露接触孔的那些位置中，蚀刻继续进入第一绝缘层，以露出图案化的导电材料的下面的第一层。通道和通孔充满金属化。通过蚀刻或化学机械（chemical-mechanical）抛光去除多余的金属化。

3. 发明授权

US5795830A Reducing pitch with continuously adjustable line and space dimensions 失效
标题翻译：减少节距，连续可调的线和空间尺寸
公开(公告)号：US5795830A
公开(公告)日：1998-08-18
申请号：US686481
申请日：1996-07-26
申请人： John E. Cronin , Carter W. Kaanta
发明人： John E. Cronin , Carter W. Kaanta
IPC分类号： H01L21/033 , H01L21/3065 , C03C25/06
CPC分类号： H01L21/0338 , H01L21/0334
摘要： A method of forming sub-lithographic elements and spaces therebetween where the pitch may be reduced with continuously adjustable line and space dimensions, and a structure resulting from the method, are disclosed. A plurality of spaced convertible members are formed on a substrate. A portion of each member is then converted, thereby reducing the dimensions of the unconverted portion of the member while increasing the width of the member plus its converted layer. A conformal layer of material is then deposited over the converted members, followed by directional etching of the conformal layer. The unconverted portion of the member is then removed. The line and space dimensions can be continuously adjusted by altering either or both of the member's converted layer and conformal layer.
摘要翻译：公开了一种在其间形成次光刻元件和间隔的方法，其中间距可以通过连续可调的线和空间尺寸减小，并且由该方法得到的结构。在基板上形成多个间隔开的可转换构件。然后将每个构件的一部分转换，从而减小构件的未转换部分的尺寸，同时增加构件加上其转换层的宽度。然后将保形层材料沉积在转换的部件上，然后定向蚀刻保形层。然后移除该成员的未转换部分。可以通过改变成员的转换层和保形层中的一个或两个来连续地调整线和空间尺寸。

4. 发明授权

US5496771A Method of making overpass mask/insulator for local interconnects 失效
标题翻译：制造用于局部互连的立交面罩/绝缘体的方法
公开(公告)号：US5496771A
公开(公告)日：1996-03-05
申请号：US245997
申请日：1994-05-19
申请人： John E. Cronin , Carter W. Kaanta , Randy W. Mann , Darrell Meulemans , Gordon S. Starkey
发明人： John E. Cronin , Carter W. Kaanta , Randy W. Mann , Darrell Meulemans , Gordon S. Starkey
IPC分类号： H01L21/768 , H01L23/522 , H01L29/49 , H01L29/78 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76895 , H01L29/4933 , Y10S257/90 , Y10S257/903 , Y10S257/915
摘要： Fabrication methods and resultant semiconductor structures wherein stack structures are selectively insulated from an enveloping layer of local interconnect material. The fabrication methods involve forming an overpass insulator(s) simultaneously with the underlying gate. Specifically, a layer of non-erodible insulating material is deposited over a layer of conductive material roughly in the area to comprise the stack structure. A simultaneous etch is then performed, and the resultant insulator portion is self-aligned to the underlying conductive material. The insulator portion insulates the stack from a subsequently deposited and planarized layer of local interconnect. Further processing options include decoupling silicide formation on selected stack structures, and various planarization and etching approaches for different available technologies. Specific details of the fabrication methods and resultant structures are set forth.
摘要翻译：制造方法和所得的半导体结构，其中堆叠结构与局部互连材料的包络层选择性地绝缘。制造方法包括与下面的栅极同时形成立交桥绝缘体。具体来说，一层不可侵蚀的绝缘材料沉积在导电材料层上，大致在该区域内以构成堆叠结构。然后执行同时蚀刻，并且所得到的绝缘体部分与下面的导电材料自对准。绝缘体部分将堆叠与随后沉积的和平坦化的局部互连层绝缘。进一步的处理选择包括在所选择的堆叠结构上去除硅化物形成，以及针对不同可用技术的各种平面化和蚀刻方法。阐述制造方法和结构结构的具体细节。

5. 发明授权

US5334467A Gray level mask 失效
标题翻译：灰度级面罩
公开(公告)号：US5334467A
公开(公告)日：1994-08-02
申请号：US22516
申请日：1993-02-25
申请人： John E. Cronin , Paul A. Farrar, Sr. , Carter W. Kaanta , James G. Ryan , Andrew J. Watts
发明人： John E. Cronin , Paul A. Farrar, Sr. , Carter W. Kaanta , James G. Ryan , Andrew J. Watts
IPC分类号： G03F1/00 , G03F7/00 , G03F9/00 , H01L21/027
CPC分类号： G03F7/0035 , G03F1/50
摘要： A gray level mask suitable for photolithography is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. The mask is fabricated with the aid of a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist, the metal of one of the layers, and the glass of the other of the layers. The etches include plasma etch with chloride ions to attack the chromium of the opaque layer, compounds of fluorine to attack the glass layer, and reactive ion etching with oxygen to attack the photoresist structure. Also, developer is employed for etching on hardened regions of resist in the photoresist structure.
摘要翻译：适用于光刻的灰度级掩模由透明玻璃基板构成，该透明玻璃基板支持具有不同透光率的多层材料。在仅使用这些水平中的两个的掩模的情况下，一个层可以由通过取代银离子代替在玻璃的结构中使用的碱金属硅酸盐的金属离子而部分透射的玻璃构成。第二层可以通过金属如铬的构造而变得不透明。借助于光致抗蚀剂结构制造掩模，该光致抗蚀剂结构通过光刻掩模在特定区域中被蚀刻，以使得能够选择性地蚀刻具有不同光学透射率的材料层的暴露区域。各种蚀刻用于选择性蚀刻光致抗蚀剂，其中一层的金属和另一层的玻璃。蚀刻包括用氯离子等离子体蚀刻以侵蚀不透明层的铬，氟的化合物侵蚀玻璃层，以及用氧反应离子蚀刻以侵蚀光致抗蚀剂结构。此外，显影剂用于蚀刻光致抗蚀剂结构中的抗蚀剂的硬化区域。

6. 发明授权

US5229257A Process for forming multi-level coplanar conductor/insulator films employing photosensitive polymide polymer compositions 失效
标题翻译：形成多层共晶导体/绝缘膜的方法使用感光聚合物聚合物组合物
公开(公告)号：US5229257A
公开(公告)日：1993-07-20
申请号：US516415
申请日：1990-04-30
申请人： John E. Cronin , Carter W. Kaanta , Pei-Ing P. Lee , Rosemary A. Previti-Kelly , James G. Ryan , Jung H. Yoon
发明人： John E. Cronin , Carter W. Kaanta , Pei-Ing P. Lee , Rosemary A. Previti-Kelly , James G. Ryan , Jung H. Yoon
IPC分类号： C08G73/10 , G03F7/038 , H01L21/312 , H01L21/768 , H01L23/522 , H05K3/00 , H05K3/04 , H05K3/10 , H05K3/46
CPC分类号： H01L21/76828 , H01L21/76807 , H01L21/76814 , H01L21/76825 , H01L23/5226 , H05K3/0023 , H05K3/467 , H01L2924/0002 , H01L2924/12044 , H05K2201/0154 , H05K3/045 , H05K3/107 , H05K3/465
摘要： Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate having a conductor pattern. The insulator layers, each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.

7. 发明授权

US5136124A Method of forming conductors within an insulating substrate 失效
标题翻译：在绝缘基板内形成导体的方法
公开(公告)号：US5136124A
公开(公告)日：1992-08-04
申请号：US585256
申请日：1990-09-19
申请人： John E. Cronin , Carter W. Kaanta , Michael A. Leach
发明人： John E. Cronin , Carter W. Kaanta , Michael A. Leach
IPC分类号： H01L21/3205 , H01L21/48 , H01L21/768 , H05K3/00 , H05K3/06 , H05K3/10 , H05K3/46
CPC分类号： H01L21/76808 , H01L21/32053 , H01L21/4846 , H01L21/76877 , H01L21/7688 , H01L2221/1031 , H01L2221/1036 , H05K3/0017 , H05K3/06 , H05K3/107 , H05K3/4644
摘要： A method for forming an electrically conductive line between two layers of insulating material and method for connecting the line through both layers of the insulating material to the opposite surfaces is provided. In the method, first, second and third layers of insulating material are provided wherein the first and third layers are separated by the second layer of insulating material which is different in etch rate from the first and third layers. The edge portion of all three layers is exposed and the insulating layer of the second material is selectively etched to remove the revealed edge portion and provide a slot between the first and third layers of insulating material. Also openings are provided in both the first and third layers of insulating material which communicate with the slot and extend respectively through the layers of the first and third insulating material. Thereafter, a conductive material such as tungsten is deposited in the slot and the openings and also on the face of the stacked insulating material. Finally, the excess tungsten is removed from the faces of the insulating material of the first and third layers leaving a conductive line sandwiched between the first and third insulating layers of the material; also metal remains in the openings formed to thereby form conductive studs extending from the line to the opposite surfaces of the insulating material sandwich so formed.
摘要翻译：提供了用于在两层绝缘材料之间形成导电线的方法以及将绝缘材料的两层连接到相对表面的方法。在该方法中，提供了绝缘材料的第一层，第二层和第三层，其中第一层和第三层由第二层绝缘材料隔开，蚀刻速率与第一层和第三层不同。暴露所有三层的边缘部分，并且选择性地蚀刻第二材料的绝缘层以去除露出的边缘部分，并在第一和第三绝缘材料层之间提供槽。在第一和第三绝缘材料层中的开口均设置有与槽连通并分别延伸穿过第一和第三绝缘材料的层。此后，诸如钨的导电材料沉积在槽和开口中以及堆叠的绝缘材料的表面上。最后，从第一和第三层的绝缘材料的表面去除多余的钨，留下夹在材料的第一和第三绝缘层之间的导线; 在形成的开口中也保留有金属，从而形成从线形延伸到形成的绝缘材料夹层的相对表面的导电柱。

8. 发明授权

US4944682A Method of forming borderless contacts 失效
标题翻译：形成无边界接触的方法
公开(公告)号：US4944682A
公开(公告)日：1990-07-31
申请号：US453368
申请日：1989-12-21
申请人： John E. Cronin , Susan F. Cronin , Carter W. Kaanta , Charles W. Koburger, III , Stephen E. Luce , Dale J. Pearson
发明人： John E. Cronin , Susan F. Cronin , Carter W. Kaanta , Charles W. Koburger, III , Stephen E. Luce , Dale J. Pearson
IPC分类号： H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/76802
摘要： A method of forming semi-conductor devices components wherein there are at least two exposed conducting regions having passivating material overlying said regions. The passivating material is subject to etching by a given etchant. At least one, but less than all of the regions are covered with a material, preferably an electrical conducting material, which also preferably covers additional electrical conducting or semi-conducting regions. Thereafter, all the regions are subjected to the given etchant, but only those regions having the passivating material not covered with the etch resistant material are removed. Preferably, at this point, a layer of conducting material is deposited over all the regions.
摘要翻译：一种形成半导体器件部件的方法，其中存在至少两个具有覆盖所述区域的钝化材料的暴露的导电区域。通过给定的蚀刻剂对钝化材料进行蚀刻。至少一个但是少于所有的区域被覆盖有优选导电材料的材料，优选地覆盖另外的导电或半导电区域。此后，对所有的区域进行给定的蚀刻剂，但是只有具有钝化材料的那些没有被抗蚀刻材料覆盖的区域被去除。优选地，在这一点上，导电材料层沉积在所有区域上。

9. 发明授权

US4758306A Stud formation method optimizing insulator gap-fill and metal hole-fill 失效
标题翻译：螺柱形成方法优化绝缘子间隙填充和金属孔填充
公开(公告)号：US4758306A
公开(公告)日：1988-07-19
申请号：US86120
申请日：1987-08-17
申请人： John E. Cronin , Carter W. Kaanta
发明人： John E. Cronin , Carter W. Kaanta
IPC分类号： H01L23/522 , H01L21/768 , B44C1/22 , C03C15/00 , C03C25/06 , C23F1/02
CPC分类号： H01L21/76885 , H01L21/76877 , Y10S438/945 , Y10S438/959
摘要： A method of forming a conductive structure on a substrate by using both of the via-filling and stud-forming metallization techniques. A stud that is approximately one-half the thickness of the final stud is defined on a conductive layer. The stud-forming mask is left in place. Then the sidewalls of the mask are positively tapered, and an insulator layer is deposited on the substrate. The insulator is then etched to expose the stud forming mask, and the mask is removed. The sidewalls of the vias thus defined in the insulator layer are then positively tapered. By positively tapering both the stud mask prior to insulator deposition and the insulator via prior to metal deposition, insulator gap-fill and metal hole-fill problems are eliminated.

10. 发明授权

US5466636A Method of forming borderless contacts using a removable mandrel 失效
标题翻译：使用可移动心轴形成无边界触点的方法
公开(公告)号：US5466636A
公开(公告)日：1995-11-14
申请号：US946993
申请日：1992-09-17
申请人： John E. Cronin , Carter W. Kaanta , Donald M. Kenney , Michael L. Kerbaugh , Howard S. Landis , Brian J. Machesney , Paul Parries , Rosemary A. Previti-Kelly , John F. Rembetski
发明人： John E. Cronin , Carter W. Kaanta , Donald M. Kenney , Michael L. Kerbaugh , Howard S. Landis , Brian J. Machesney , Paul Parries , Rosemary A. Previti-Kelly , John F. Rembetski
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L29/417 , H01L21/44
CPC分类号： H01L27/10861 , H01L21/76838 , H01L21/76897 , H01L29/41766 , Y10S438/943
摘要： A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).
摘要翻译：一种用于使用可移除心轴（110）形成无边界触点（130,170,172）的半导体制造工艺。该方法包括将心轴沉积在设计成保护形成在基底（24）上的下面的结构（40）的下面的阻挡层（100）上。心轴由将以比阻挡层更快的速度蚀刻的材料制成，以允许心轴中的开口形成停止在阻挡层上而不穿透该层。在将形成在心轴中的第一开口（120）中的接触（130）沉积之后，形成第二开口（140），并且在其中沉积第二接触（170）。此后，移去心轴并用一层固体电介质材料（180）代替。

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