专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08564317B2 Test socket, and test apparatus with test socket to control a temperature of an object to be tested 有权
标题翻译：测试插座和带有测试插座的测试设备，用于控制待测物体的温度
公开(公告)号：US08564317B2
公开(公告)日：2013-10-22
申请号：US12719267
申请日：2010-03-08
申请人： Jong-Won Han , Seok Goh , Byoung-Jun Min , Jung-Hyeon Kim , Sang-Sik Lee , Bo-Woo Kim , Ho-Jeong Choi
发明人： Jong-Won Han , Seok Goh , Byoung-Jun Min , Jung-Hyeon Kim , Sang-Sik Lee , Bo-Woo Kim , Ho-Jeong Choi
IPC分类号： G01R31/00
CPC分类号： G01R1/0458 , G01R31/2863 , G01R31/2875
摘要： A test socket is provided that includes a socket body to receive an object to be tested, a lid disposed on the socket body, one or more pushers coupled to a first surface of lid to apply force to a first surface of the object toward the socket body, and a temperature controlling member to provide a temperature to the object. A semiconductor package may be tested in a test apparatus that includes the test socket, the methods of testing including receiving a semiconductor package in a socket in a test chamber, applying a first temperature to the test chamber to test the semiconductor package at a first test temperature, and applying a second temperature to the semiconductor package to test the semiconductor package at a second test temperature by controlling the application of the second temperature with the socket.
摘要翻译：提供了一种测试插座，其包括用于接收被测试对象的插座主体，设置在插座主体上的盖子，一个或多个连接到盖的第一表面的推动器，以向该插座的第一表面施加力主体和温度控制构件以向对象提供温度。可以在包括测试插座的测试设备中测试半导体封装，测试方法包括在测试室中的插座中接收半导体封装，将第一温度施加到测试室以在第一测试中测试半导体封装温度，并且向半导体封装施加第二温度以通过控制第二温度与插座的应用来在第二测试温度下测试半导体封装。

2. 发明申请

US20080164901A1 Multilayer type test board assembly for high-precision inspection 有权
标题翻译：多层型测试板组件进行高精度检测
公开(公告)号：US20080164901A1
公开(公告)日：2008-07-10
申请号：US12006543
申请日：2008-01-03
申请人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
发明人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
IPC分类号： G01R1/02
CPC分类号： G01R31/2851 , G01R1/04 , H05K1/144 , H05K1/148 , H05K2201/042 , H05K2201/09972 , H05K2201/10371
摘要： There is provided a multilayer type test board assembly for high-precision inspection. The multilayer test board assembly comprises: a plurality of test boards separated from each other according to their functions, having input/output signal terminals, and including at least one test board each having a first section where first mounting devices sensitive to an influence of electrical signals are mounted and a second section where second mounting devices insensitive to an influence of electrical signals are mounted; spacers that arrange the test boards in parallel by spacing apart the test boards by predetermined intervals; connection cables connected to the input/output signal terminals of the test boards; and a signal shielding fence formed on each of the at least one test board so as to protect the first mounting devices from electrical signals generated by the second mounting devices.
摘要翻译：提供了一种用于高精度检测的多层型测试板组件。多层测试板组件包括：根据功能彼此分离的多个测试板，具有输入/输出信号端子，并且包括至少一个测试板，每个测试板具有第一部分，其中第一安装器件对电气的影响敏感信号被安装，并且第二部分安装对电信号的影响不敏感的第二安装装置; 间隔件通过以预定的间隔隔开测试板来平行布置测试板; 连接电缆连接到测试板的输入/输出信号端子; 以及形成在所述至少一个测试板中的每一个上的信号屏蔽栅栏，以便保护所述第一安装装置免受由所述第二安装装置产生的电信号。

3. 发明申请

US20080164894A1 System and method for testing semiconductor integrated circuit in parallel 审中-公开
标题翻译：半导体集成电路并行测试的系统和方法
公开(公告)号：US20080164894A1
公开(公告)日：2008-07-10
申请号：US12006560
申请日：2008-01-03
申请人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
发明人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
IPC分类号： G01R31/26
CPC分类号： G01R31/2886 , G01R31/2889
摘要： A system and method for testing a semiconductor integrated circuit (IC) in parallel includes a probe chuck, a test head, and a test controller. The probe chuck loads a plurality of different types of semiconductor DUTs. The test head provides a plurality of circuit sites to independently and simultaneously test the different types of semiconductor DUTs, and the test controller controls the test head and the probe chuck.
摘要翻译：用于同时测试半导体集成电路（IC）的系统和方法包括探针卡盘，测试头和测试控制器。探头卡盘装载多种不同类型的半导体DUT。测试头提供多个电路位置，以独立并同时测试不同类型的半导体DUT，并且测试控制器控制测试头和探头卡盘。

4. 发明授权

US07786721B2 Multilayer type test board assembly for high-precision inspection 有权
标题翻译：多层型测试板组件进行高精度检测
公开(公告)号：US07786721B2
公开(公告)日：2010-08-31
申请号：US12006543
申请日：2008-01-03
申请人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
发明人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2851 , G01R1/04 , H05K1/144 , H05K1/148 , H05K2201/042 , H05K2201/09972 , H05K2201/10371
摘要： There is provided a multilayer type test board assembly for high-precision inspection. The multilayer test board assembly comprises: a plurality of test boards separated from each other according to their functions, having input/output signal terminals, and including at least one test board each having a first section where first mounting devices sensitive to an influence of electrical signals are mounted and a second section where second mounting devices insensitive to an influence of electrical signals are mounted; spacers that arrange the test boards in parallel by spacing apart the test boards by predetermined intervals; connection cables connected to the input/output signal terminals of the test boards; and a signal shielding fence formed on each of the at least one test board so as to protect the first mounting devices from electrical signals generated by the second mounting devices.
摘要翻译：提供了一种用于高精度检测的多层型测试板组件。多层测试板组件包括：根据功能彼此分离的多个测试板，具有输入/输出信号端子，并且包括至少一个测试板，每个测试板具有第一部分，其中第一安装装置对电气的影响敏感信号被安装，并且第二部分安装对电信号的影响不敏感的第二安装装置; 间隔件通过以预定的间隔隔开测试板来平行布置测试板; 连接电缆连接到测试板的输入/输出信号端子; 以及形成在所述至少一个测试板中的每一个上的信号屏蔽栅栏，以便保护所述第一安装装置免受由所述第二安装装置产生的电信号。

5. 发明申请

US20080164898A1 Probe card for test of semiconductor chips and method for test of semiconductor chips using the same 审中-公开
标题翻译：用于半导体芯片测试的探针卡和使用其的半导体芯片的测试方法
公开(公告)号：US20080164898A1
公开(公告)日：2008-07-10
申请号：US12005888
申请日：2007-12-28
申请人： Sung-Hoon Bae , Jung-Hyeon Kim , Young-Soo An , Ho-Jeong Choi , Myoung-Sub Kim
发明人： Sung-Hoon Bae , Jung-Hyeon Kim , Young-Soo An , Ho-Jeong Choi , Myoung-Sub Kim
IPC分类号： G01R31/02
CPC分类号： G01R1/07385 , G01R1/07342
摘要： There are provided a probe card for test of semiconductor chips and a method for testing semiconductor chips using the probe card. In implementing the probe card for electrically testing semiconductor chips, the probe blocks corresponding to multiple selected ones of the semiconductor chips on the wafer can be selected so that the selected semiconductor chips are EDS tested in a one-step process. As the selected semiconductor chips are EDS tested in a one-step process, equipment efficiency is improved, and statistical objectivity of data indicating characteristics of the wafer can be achieved.
摘要翻译：提供了用于半导体芯片测试的探针卡和使用探针卡测试半导体芯片的方法。在实现用于电测试半导体芯片的探针卡时，可以选择对应于晶片上的多个选定的半导体芯片的探针块，使得所选择的半导体芯片在一步法中进行EDS测试。由于所选择的半导体芯片在一步法中进行了EDS测试，所以提高了设备效率，并且可以实现表示晶片特性的数据的统计客观性。

6. 发明授权

US08547766B2 Area-efficient data line layouts to suppress the degradation of electrical characteristics 有权
标题翻译：区域高效的数据线布局，以抑制电气特性的恶化
公开(公告)号：US08547766B2
公开(公告)日：2013-10-01
申请号：US12659883
申请日：2010-03-24
申请人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C11/4097
摘要： A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
摘要翻译：数据线布局包括在存储单元阵列区域上的层上沿着第一方向布置的列选择线以及沿着该层的第一方向布置的数据线，数据线连接在I / O读出放大器和I / O之间垫

7. 发明授权

US08187914B2 Methods of forming a phase change memory device 有权
标题翻译：形成相变存储器件的方法
公开(公告)号：US08187914B2
公开(公告)日：2012-05-29
申请号：US12731637
申请日：2010-03-25
申请人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Young-Lim Park , Jung-Hyeon Kim
发明人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Young-Lim Park , Jung-Hyeon Kim
IPC分类号： H01L21/20
CPC分类号： H01L45/1616 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.
摘要翻译：提供形成相变存储器件的方法。可以制备具有下电极和层间绝缘层的半导体器件。下电极可以被层间绝缘层包围。可以将源气体，反应气体和吹扫气体注入到半导体制造装置的处理室中，以在半导体衬底上形成相变材料层。源气体可以同时注入到处理室中。相变材料层可以通过层间绝缘层与下电极接触。可以蚀刻相变材料层以在层间绝缘层中形成相变存储单元。可以在相变存储单元上形成上电极。

8. 发明授权

US08130577B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08130577B2
公开(公告)日：2012-03-06
申请号：US12590417
申请日：2009-11-06
申请人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/08 , G11C5/025 , G11C7/1012 , G11C7/12 , G11C2207/002
摘要： A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line.
摘要翻译：半导体存储器件包括具有存储单元的子存储单元阵列区域，每个存储单元分别连接在沿第一方向延伸的字线和沿着与字线的第一延伸方向正交的第二方向延伸的位线和一个子字线驱动器区域，设置在副存储单元阵列区域的第一方向的一侧，并且包括激活字线的子字线驱动器。感测区域设置在副存储单元阵列区域的第二方向的一侧，并且包括响应于通过驱动信号线传送的信号而对位线进行预充电的均衡器，以及至少一个第一控制信号驱动器，其激活响应于通过控制信号线传送的信号的反相控制信号线。配置在副字线驱动器区域和感测区域之间的交叉点处的连接区域，其中反相控制信号线连接到驱动信号线。

9. 发明授权

US07906423B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07906423B2
公开(公告)日：2011-03-15
申请号：US12650093
申请日：2009-12-30
申请人： Hyo-Jae Bang , Heui-Seog Kim , Dong-Chun Lee , Seong-Chan Han , Jung-Hyeon Kim
发明人： Hyo-Jae Bang , Heui-Seog Kim , Dong-Chun Lee , Seong-Chan Han , Jung-Hyeon Kim
IPC分类号： H01L21/44
CPC分类号： H05K3/303 , H05K2201/0305 , H05K2201/09781 , H05K2201/10689 , H05K2201/2036 , Y02P70/613
摘要： A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.
摘要翻译：半导体器件包括半导体封装，电路板和间隔保持元件。半导体封装具有从主体突出的主体和引线。电路板具有与引线电连接的第一焊盘。间隔保持构件插入在电路板和主体之间。间隔保持构件保持引线与第一焊盘之间的间隔。因此，均匀地保持引线和焊盘之间的间隔，从而提高了半导体器件的热和/或机械可靠性。

10. 发明授权

US07841505B2 Wire clamp and wire bonding apparatus having the same 有权
标题翻译：具有相同的线夹和引线接合装置
公开(公告)号：US07841505B2
公开(公告)日：2010-11-30
申请号：US12320964
申请日：2009-02-10
申请人： Sung-Soo Lee , Ki-Taik Oh , Jung-Hyeon Kim
发明人： Sung-Soo Lee , Ki-Taik Oh , Jung-Hyeon Kim
IPC分类号： B23K37/00
CPC分类号： H01L24/85 , B23K20/007 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/45144 , H01L2224/48227 , H01L2224/48463 , H01L2224/78301 , H01L2224/786 , H01L2224/851 , H01L2224/85205 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A wire clamp includes a pair of clamp arms at a predetermined distance from each other to define an interval therebetween for a bonding wire, a clamp body coupled to the clamp arms, the clamp body configured to adjust the predetermined distance between the clamp arms with respect to a process to be performed, a clamping section in each clamp arm, the clamping section having concave portions facing the interval between the clamp arms, the concave portions being configured to contact the bonding wire when the clamp arms are brought close together, and at least one abrasion prevention member in each clamping section, the abrasion prevention members being configured to prevent abrasion during contact with the bonding wire.
摘要翻译：电线夹具包括彼此隔开预定距离的一对夹持臂，以在其间限定用于接合线的间隔，联接到夹紧臂的夹具本体，夹具主体被配置为相对于夹具臂之间的预定距离调整对于要执行的处理，每个夹持臂中的夹持部分，夹持部分具有面对夹紧臂之间的间隔的凹部，凹部被构造成在夹紧臂靠近在一起时与接合线接触，并且在每个夹紧部分中的至少一个防磨损构件，所述防磨构件被构造成防止在与所述接合线接触期间的磨损。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式