专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08564317B2 Test socket, and test apparatus with test socket to control a temperature of an object to be tested 有权
标题翻译：测试插座和带有测试插座的测试设备，用于控制待测物体的温度
公开(公告)号：US08564317B2
公开(公告)日：2013-10-22
申请号：US12719267
申请日：2010-03-08
申请人： Jong-Won Han , Seok Goh , Byoung-Jun Min , Jung-Hyeon Kim , Sang-Sik Lee , Bo-Woo Kim , Ho-Jeong Choi
发明人： Jong-Won Han , Seok Goh , Byoung-Jun Min , Jung-Hyeon Kim , Sang-Sik Lee , Bo-Woo Kim , Ho-Jeong Choi
IPC分类号： G01R31/00
CPC分类号： G01R1/0458 , G01R31/2863 , G01R31/2875
摘要： A test socket is provided that includes a socket body to receive an object to be tested, a lid disposed on the socket body, one or more pushers coupled to a first surface of lid to apply force to a first surface of the object toward the socket body, and a temperature controlling member to provide a temperature to the object. A semiconductor package may be tested in a test apparatus that includes the test socket, the methods of testing including receiving a semiconductor package in a socket in a test chamber, applying a first temperature to the test chamber to test the semiconductor package at a first test temperature, and applying a second temperature to the semiconductor package to test the semiconductor package at a second test temperature by controlling the application of the second temperature with the socket.
摘要翻译：提供了一种测试插座，其包括用于接收被测试对象的插座主体，设置在插座主体上的盖子，一个或多个连接到盖的第一表面的推动器，以向该插座的第一表面施加力主体和温度控制构件以向对象提供温度。可以在包括测试插座的测试设备中测试半导体封装，测试方法包括在测试室中的插座中接收半导体封装，将第一温度施加到测试室以在第一测试中测试半导体封装温度，并且向半导体封装施加第二温度以通过控制第二温度与插座的应用来在第二测试温度下测试半导体封装。

2. 发明申请

US20090009204A1 Test socket 审中-公开
标题翻译：测试插座
公开(公告)号：US20090009204A1
公开(公告)日：2009-01-08
申请号：US12214932
申请日：2008-06-24
申请人： Sang-Sik Lee , Bo-Woo Kim , Ho-Jeong Choi
发明人： Sang-Sik Lee , Bo-Woo Kim , Ho-Jeong Choi
IPC分类号： G01R31/02
CPC分类号： G01R1/0458 , G01R31/2875
摘要： A test socket in accordance with one aspect of the present invention includes a socket body, a thermoelectric element and a heat transfer member. The socket body receives an object. The thermoelectric element is arranged in the socket body to emit heat and absorb heat in accordance with current directions. The heat transfer member is arranged between the object and the thermoelectric element to transfer a heat generated from the object to the thermoelectric element. Thus, the object may be directly provided with a desired test temperature using the thermoelectric element so that the desired test temperature may be set rapidly and accurately. Further, the heat transfer member interposed between the object and the thermoelectric element may quickly dissipate the heat in the object.
摘要翻译：根据本发明的一个方面的测试插座包括插座体，热电元件和传热构件。插座主体接收一个对象。热电元件布置在插座主体中以发射热量并根据电流方向吸收热量。传热构件设置在物体和热电元件之间，以将从物体产生的热量传递到热电元件。因此，可以使用热电元件将物体直接设置有期望的测试温度，使得可以快速且准确地设置期望的测试温度。此外，介于物体和热电元件之间的传热构件可能会快速地散发物体中的热量。

3. 发明授权

US5500389A Process for formation for hetero junction structured film utilizing V grooves 失效
标题翻译：利用V沟槽形成异质结结构薄膜的工艺
公开(公告)号：US5500389A
公开(公告)日：1996-03-19
申请号：US342031
申请日：1994-11-17
申请人： Seung-Chang Lee , Sun-Jin Yun , Bo-Woo Kim , Sang-Won Kang
发明人： Seung-Chang Lee , Sun-Jin Yun , Bo-Woo Kim , Sang-Won Kang
IPC分类号： B82Y10/00 , B82Y40/00 , H01L21/20 , H01L21/203
CPC分类号： H01L33/025 , H01L21/0243 , H01L21/02532 , H01L21/02639 , H01L33/002 , Y10S438/938
摘要： A process for formation of a hetero junction structured film utilizing V grooves is disclosed. A monocrystalline film 1 is etched into V grooves, and thereupon, a hetero film 2 having misfits is grown, so that dislocations would be intensively distributed within the V grooves. Then, an oxide layer 3 is formed thereupon, and then, the portions of the oxide layer 3 and the hereto film 2 corresponding to the V grooves are removed by carrying out an etching. Then, the residue oxide layer is removed, thereby forming a non-stress non-dislocation hetero junction structure. Further, the following steps can be added. That is, on the above structure, a thin oxide layer 3 is deposited by carrying out a thermal oxidation or a chemical deposition, and then, a polycrystalline silicon film 4 is deposited. Then the surface irregularities are smoothened by carrying out a selective grinding. Or the following steps may be added. That is, the V groove portions of the hetero film 2 and the monocrystalline film 1 are filled with a monocrystalline film, and the residue oxide layer 3 is removed. Thus a hetero junction film can be grown in which the stress effect is minimized, and the dislocation concentration is made to be extremely low.
摘要翻译：公开了一种利用V沟形成异质结结构薄膜的方法。将单晶膜1蚀刻成V槽，随后生长出错位的异质膜2，使位错集中分布在V槽内。然后，在其上形成氧化物层3，然后通过进行蚀刻来去除与V槽对应的氧化物层3和本膜2的部分。然后，除去残留氧化物层，从而形成非应力非位错异质结结构。此外，可以添加以下步骤。也就是说，在上述结构中，通过进行热氧化或化学沉积来沉积薄的氧化物层3，然后沉积多晶硅膜4。然后通过进行选择性研磨使表面凹凸平滑。或者可以添加以下步骤。也就是说，异质膜2和单晶膜1的V槽部分填充有单晶膜，并且去除残余氧化物层3。因此，可以生长应力效应最小化的异质结膜，并使位错浓度极低。

4. 发明授权

US6147896A Nonvolatile ferroelectric memory using selective reference cell 有权
标题翻译：使用选择性参考电池的非易失性铁电存储器
公开(公告)号：US6147896A
公开(公告)日：2000-11-14
申请号：US429752
申请日：1999-10-28
申请人： Shi-Ho Kim , Bo-Woo Kim , Byoung-Gon Yu , Won-Jae Lee
发明人： Shi-Ho Kim , Bo-Woo Kim , Byoung-Gon Yu , Won-Jae Lee
IPC分类号： G11C7/06 , G11C11/22
CPC分类号： G11C11/22
摘要： A nonvolatile ferroelectric memory that reduces the number of cycles of reference cells to extend lifetime of memory. A reference cell of the memory is activated to provide a reference voltage to a sense amplifier only when the sense amplifier needs the reference voltage. The memory comprises a plurality of cells arranged in a matrix form and including memory cells and reference cells, and a plurality of sense amplifiers arranged in a row of the matrix, in which each sense amplifier compares voltages induced from a reference cell and a selected memory cell to read information stored in the selected memory cell, and in which each reference cell is activated only when both a selection signal from a column address and a word line connected to said reference cell are enabled.
摘要翻译：一种非易失性铁电存储器，其减少参考单元的周期数以延长存储器的使用寿命。仅当感测放大器需要参考电压时，激活存储器的参考单元才能向读出放大器提供参考电压。存储器包括以矩阵形式布置并且包括存储器单元和参考单元的多个单元以及布置在矩阵的一行中的多个读出放大器，其中每个读出放大器将从参考单元引起的电压和所选择的存储器进行比较单元读取存储在所选择的存储器单元中的信息，并且其中每个参考单元仅当来自列地址的选择信号和连接到所述参考单元的字线都被使能时被激活。

5. 发明授权

US5453398A Method for fabricating quantum wire laser diode 失效
标题翻译：量子线激光二极管的制造方法
公开(公告)号：US5453398A
公开(公告)日：1995-09-26
申请号：US335453
申请日：1994-11-07
申请人： Hae-Gwon Lee , Jae-Jin Lee , Bo-Woo Kim
发明人： Hae-Gwon Lee , Jae-Jin Lee , Bo-Woo Kim
IPC分类号： H01L33/06 , H01L33/20 , H01L33/30 , H01L33/36 , H01S5/00 , H01S5/20 , H01S5/34 , H01S5/343 , H01L21/20
CPC分类号： H01S5/341 , B82Y20/00 , H01S2304/02 , H01S5/2081 , H01S5/3432 , Y10S438/962
摘要： Disclosed is a fabricating method of a quantum wire laser diode, comprising the steps of preparing a GaAs substrate; sequentially forming n-type epitaxial layers and a first photoresist layer on the GaAs substrate; removing a portion of the intrinsic GaAs layer by using a first etching solution, and then removing the photoresist layer; wet-etching away a portion of the intrinsic AlAs layer in the vicinity of the opening by using a second etching solution; growing a quantum structure in the molecular beam epitaxy apparatus to form a multiple quantum well on the intrinsic GaAs layer and form a quantum wire on the n-type energy band slope layer through the opening; removing the quantum well, the intrinsic GaAs layer and the intrinsic AlAs layer simultaneously by using a third etching solution; sequentially forming a p-type energy band slope layer, a p-type cladding layer and a p.sup.+ -GaAs layer, on the n-type energy band slope layer and the quantum wire, and forming a second photoresist layer having a predetermined pattern on the p.sup.+ -GaAs layer; removing the layers laminated on the n-type resistive contact layer using the second photoresist layer patterned thus as an etching mask and then removing the second photoresist layer; and forming an n-type ohmic contact metal on the n-type resistive contact layer and a p-type ohmic contact metal on the p.sup.+ -GaAs layer. By this method, because a quantum well formed near to a quantum wire therein is simultaneously removed during removal of other epitaxial layers, another etching process is not required for removing only the quantum well.
摘要翻译：公开了一种量子线激光二极管的制造方法，包括以下步骤：制备GaAs衬底; 在GaAs衬底上依次形成n型外延层和第一光致抗蚀剂层; 通过使用第一蚀刻溶液去除本征GaAs层的一部分，然后除去光致抗蚀剂层; 通过使用第二蚀刻溶液湿蚀刻在开口附近的本征AlAs层的一部分; 在分子束外延装置中生长量子结构，在本征GaAs层上形成多量子阱，并通过开口在n型能带斜率层上形成量子线; 通过使用第三蚀刻溶液同时去除量子阱，本征GaAs层和本征AlAs层; 在n型能带斜率层和量子线上依次形成p型能带斜率层，p型包覆层和p + -GaAs层，并在其上形成具有预定图案的第二光致抗蚀剂层 p + -GaAs层; 使用图案化为蚀刻掩模的第二光致抗蚀剂层去除层压在n型电阻接触层上的层，然后除去第二光致抗蚀剂层; 在n型电阻接触层上形成n型欧姆接触金属，在p + -GaAs层上形成p型欧姆接触金属。通过该方法，由于在去除其它外延层期间同时去除在其内的量子线附近形成的量子阱，因此不需要另外的蚀刻工艺来仅去除量子阱。

6. 发明授权

US5693555A Method for fabricating BiCMOS device 失效
标题翻译： BiCMOS器件制造方法
公开(公告)号：US5693555A
公开(公告)日：1997-12-02
申请号：US670756
申请日：1996-06-21
申请人： Kwang-Soo Kim , Cheon-Soo Kim , Kyu-Ha Baek , Bo-Woo Kim
发明人： Kwang-Soo Kim , Cheon-Soo Kim , Kyu-Ha Baek , Bo-Woo Kim
IPC分类号： H01L21/822 , H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A method for fabricating a bipolar complementary metal oxide semiconductor device, includes a first step of forming a three-layered substrate of p.sup.- /n.sup.+ /n.sup.- type or n.sup.- /p.sup.+ /p.sup.- type and forming p- and n-wells to be adjacent to each other to the bottom of the top layer of the three-layered substrate; a second step of isolating the p- and n-wells from each other and defining a region for a bipolar transistor on one side to separate base/emitter regions from each other; a third step of defining a gate region to form a metal- oxide semiconductor transistor in each of the p- and n-wells and forming collector/emitter regions in the bipolar transistor region; and a fourth step of forming an n-type metal oxide semiconductor transistor, a p-type metal oxide semiconductor transistor and a bipolar transistor on the p-well, n-well and collector/emitter regions, respectively, and forming source/drain and base electrodes through diffusion by using a doped polycrystalline silicon sidewall spacer.
摘要翻译：一种制造双极互补金属氧化物半导体器件的方法，包括：形成p / n + / n型或n / p + / p-型三层衬底并形成p-和n-阱的第一步骤彼此相邻到三层基板的顶层的底部; 将p阱和n阱彼此隔离并且在一侧限定双极晶体管的区域以将基极/发射极区彼此分离的第二步骤; 限定栅极区以在所述p阱和n阱中的每一个中形成金属氧化物半导体晶体管并在所述双极晶体管区域中形成集电极/发射极区域的第三步骤; 以及分别在p阱，n阱和集电极/发射极区域上形成n型金属氧化物半导体晶体管，p型金属氧化物半导体晶体管和双极晶体管的第四步骤，并且形成源极/漏极和通过使用掺杂的多晶硅侧壁间隔物扩散基底电极。

7. 发明授权

US5406505A Method of and apparatus for measuring energy gap of semiconductor 失效
标题翻译：测量半导体能隙的方法和装置
公开(公告)号：US5406505A
公开(公告)日：1995-04-11
申请号：US994593
申请日：1992-12-15
申请人： Seong-Jun Kang , Bo-Woo Kim , Yil-Sung Bae
发明人： Seong-Jun Kang , Bo-Woo Kim , Yil-Sung Bae
IPC分类号： G01N21/35 , G01N21/62
CPC分类号： G01N21/3563
摘要： A method and apparatus is disclosed for measuring an energy gap of a semiconductor material. The method contains the steps of analyzing a character of a reference semiconductor sample and setting an energy gap pixel value, estimating a transfer function between the pixel value, positioning the sample properly and imaging the spectrum to obtain a live image, storing the live image and scanning the respective pixel values along an x-axis of the image, sequentially comparing the respective pixel value and the energy gap pixel value, reading an x-coordinate of the pixel and converting the wavelength of the pixel to estimate the energy gap. The apparatus optically measures the energy gap and comprises a light source irradiating a light beam, a lens for focusing the light beam, a polychromator for irradiating the spectrum of light of the light beam to the sample, optical filters for evaluating a spectrum band of the polychromator into wavelength values, an image acquisition apparatus, an image signal processor, an energy gap detecting and displaying apparatus, and a computer for executing operation and control functions necessary to measure the energy gap by use of the image signal processor and the energy gap detecting and displaying apparatus.
摘要翻译：公开了一种用于测量半导体材料的能隙的方法和装置。该方法包括以下步骤：分析参考半导体样本的字符并设置能隙像素值，估计像素值之间的传递函数，适当地定位样本并成像光谱以获得实时图像，存储实时图像;以及沿着图像的x轴扫描各个像素值，顺序地比较各个像素值和能隙像素值，读取像素的x坐标并转换像素的波长以估计能隙。该设备光学测量能隙并包括照射光束的光源，用于聚焦光束的透镜，用于将光束的光束照射到样品的多色分光器，用于评估光束的光谱带的光学滤光器多色分光子变为波长值，图像采集装置，图像信号处理器，能隙检测和显示装置，以及用于执行通过使用图像信号处理器和能隙检测来测量能隙所需的操作和控制功能的计算机和显示装置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式