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1. 发明授权

US07738573B2 System and method for crest factor reduction 有权
标题翻译：波峰因数降低的系统和方法
公开(公告)号：US07738573B2
公开(公告)日：2010-06-15
申请号：US11246027
申请日：2005-10-07
申请人： Khiem V. Cai , Samuel Davis Kent, III , Don C. Devendorf
发明人： Khiem V. Cai , Samuel Davis Kent, III , Don C. Devendorf
IPC分类号： H04K1/10
CPC分类号： H04L27/2624
摘要： A crest reduction system and method. The inventive system includes a first circuit for suppressing peak amplitudes of an input signal and providing a peak amplitude suppressed signal in response thereto and a second circuit coupled to the first circuit for rejecting intermodulation distortion in the amplitude suppressed signal. In the illustrative implementation, the first circuit is a peak amplitude suppressor having circuitry for computing an amplitude of the input signal and for computing a gain factor for the input signal in response thereto. In the best mode, the gain factor is obtained from a lookup table. The peak amplitude suppressor further includes a multiplier for applying the gain factor to the input signal. In the illustrative embodiment, the second circuit includes a plurality of bandpass filters and a summer for combining the outputs thereof.
摘要翻译：一种降幅系统和方法。本发明的系统包括：第一电路，用于抑制输入信号的峰值振幅并响应于此提供峰值振幅抑制信号;以及第二电路，耦合到第一电路，用于抑制振幅抑制信号中的互调失真。在说明性实现中，第一电路是峰值幅度抑制器，其具有用于计算输入信号的幅度的电路，并且响应于此计算输入信号的增益因子。在最佳模式下，增益因子从查找表获得。峰值幅度抑制器还包括用于将增益因子应用于输入信号的乘法器。在说明性实施例中，第二电路包括多个带通滤波器和用于组合其输出的加法器。

2. 发明申请

US20110059710A1 DYNAMIC CREST FACTOR REDUCTION SYSTEM 审中-公开
标题翻译：动态冲击因子减少系统
公开(公告)号：US20110059710A1
公开(公告)日：2011-03-10
申请号：US12945104
申请日：2010-11-12
申请人： Khiem V. Cai , Samuel Davis Kent, III
发明人： Khiem V. Cai , Samuel Davis Kent, III
IPC分类号： H04B7/00
CPC分类号： H04L27/2623
摘要： A system and method for performing digital crest factor reduction. In one embodiment, the method is devised to suppress the signal amplitude to maintain a low signal peak to average ratio (PAR), while maintaining a desirable Error Vector Magnitude (EVM). This technique may be designed to operate in highly dynamic signal conditions.
摘要翻译：一种用于执行数字波峰因数降低的系统和方法。在一个实施例中，该方法被设计为抑制信号幅度以保持低信号峰值平均比（PAR），同时保持期望的误差矢量幅度（EVM）。该技术可以设计成在高度动态的信号条件下工作。

3. 发明授权

US07839951B2 Dynamic crest factor reduction system 有权
标题翻译：动态波峰因数降低系统
公开(公告)号：US07839951B2
公开(公告)日：2010-11-23
申请号：US11784433
申请日：2007-04-05
申请人： Khiem V. Cai , Samuel Davis Kent, III
发明人： Khiem V. Cai , Samuel Davis Kent, III
IPC分类号： H04K1/02
CPC分类号： H04L27/2623
摘要： A system and method for performing digital crest factor reduction. In one embodiment, the method is devised to suppress the signal amplitude to maintain a low signal peak to average ratio (PAR), while maintaining a desirable Error Vector Magnitude (EVM). This technique may be designed to operate in highly dynamic signal conditions.
摘要翻译：一种用于执行数字波峰因数降低的系统和方法。在一个实施例中，该方法被设计为抑制信号幅度以保持低信号峰值平均比（PAR），同时保持期望的误差矢量幅度（EVM）。该技术可以设计成在高度动态的信号条件下工作。

4. 发明授权

US07809081B2 Digital pre-distortion technique using nonlinear filters 有权
标题翻译：使用非线性滤波器的数字预失真技术
公开(公告)号：US07809081B2
公开(公告)日：2010-10-05
申请号：US12574796
申请日：2009-10-07
申请人： Khiem V. Cai , David B. Rutan , Matthew S. Gorder , Don C. Devendorf
发明人： Khiem V. Cai , David B. Rutan , Matthew S. Gorder , Don C. Devendorf
IPC分类号： H04K1/02
CPC分类号： H04L25/03885 , H03F1/3247 , H03F1/3276 , H04L25/49 , H04L27/2626 , H04L27/368
摘要： A method and computer program product for operating a linearizer for a circuit, including generating a set of coefficients via a characterizer; predistorting a signal input to the circuit responsive to the coefficients and generating a linearized output in response thereto; filtering the signal through a linear digital filter having linear digital filter taps, each tap other than a first tap being successively delayed by one delay unit; generating powers of the signal; inputting the generated powers of the signal through tapped delay lines, each line having nonlinear digital filter taps, each tap other than a first tap being successively delayed by one delay unit; applying the coefficients to the linear and nonlinear digital filter taps; summing each of the nonlinear digital filter taps corresponding to a certain number of delay units; and adding the sum of each of the delay units to a particular linear digital filter tap.
摘要翻译：一种用于操作电路的线性化器的方法和计算机程序产品，包括经由表征器生成一组系数; 响应于系数预失真输入到电路的信号并响应于此产生线性化的输出; 通过具有线性数字滤波器抽头的线性数字滤波器对信号进行滤波，除了连续延迟一个延迟单元的第一抽头以外的每个抽头; 产生信号的功率; 通过抽头延迟线输入信号的发生功率，每行具有非线性数字滤波器抽头，每个抽头不同于连续延迟一个延迟单元的第一抽头; 将系数应用于线性和非线性数字滤波器抽头; 对与一定数量的延迟单元相对应的每个非线性数字滤波器抽头相加; 并将每个延迟单元的和加到特定的线性数字滤波器抽头上。

5. 发明授权

US5572220A Technique to detect angle of arrival with low ambiguity 失效
标题翻译：以低模糊度检测到达视角的技术
公开(公告)号：US5572220A
公开(公告)日：1996-11-05
申请号：US443537
申请日：1995-05-18
申请人： Khiem V. Cai
发明人： Khiem V. Cai
IPC分类号： G01S3/04 , G01S3/46 , G01S5/04
CPC分类号： G01S3/46 , G01S3/043
摘要： An angle-of-arrival (AOA) phase unwrapping technique using a trellis search to determine the correct AOA. An antenna array having several elements arranged to establish several baselines (element spacings) between different pairs of elements receives RF signals, ranging from 1/2 .lambda. to multiples of 1/2 .lambda.. The search starts from the smallest baseline to determine the unambiguous unwrapped phase. From this least unambiguous unwrapped phase, the process then searches for the closest unwrapped phase on the second smallest baseline, eliminating the ambiguity, and improving the accuracy. As the search processes the larger baselines, the accuracy is increased, while controlling the ambiguity. As a result, the largest baseline yields the most accurate and unambiguous AOA, and results in maximum likelihood estimation of AOA.
摘要翻译：到达角（AOA）相位展开技术使用网格搜索来确定正确的AOA。具有布置成在不同元件对之间建立几个基线（元件间隔）的若干元件的天线阵列接收范围从1/2λ到1/2λ倍数的RF信号。搜索从最小基线开始，以确定明确的展开相位。从这个最小的无歧义展开阶段，该过程然后在第二个最小基线上搜索最接近的展开相位，消除模糊性，并提高精度。随着搜索过程的更大基线，准确性增加，同时控制歧义。因此，最大的基线产生最准确和明确的AOA，并导致AOA的最大似然估计。

6. 发明授权

US5267272A Receiver automatic gain control (AGC) 失效
标题翻译：接收机自动增益控制（AGC）
公开(公告)号：US5267272A
公开(公告)日：1993-11-30
申请号：US655684
申请日：1991-02-14
申请人： Khiem V. Cai , James L. Thomas , Patrick L. Lim
发明人： Khiem V. Cai , James L. Thomas , Patrick L. Lim
IPC分类号： H03G3/20 , H04B1/713 , H04B1/715 , H04L27/08
CPC分类号： H04B1/715 , H03G3/3052 , H03G3/3073 , H04B1/713 , H04B2001/7152
摘要： The invention is an automatic gain control (AGC) sampling structure in which a conventional closed loop AGC circuit detects a received level and generates a direct current voltage for controlling an amplification stage. This direct current voltage is sampled and the optimum control voltage is selected from the samples based on the technique of ordered statistics. The conventional AGC control loop is interrupted and the selected control voltage is provided to the amplification stage.
摘要翻译：本发明是一种自动增益控制（AGC）采样结构，其中常规闭环AGC电路检测接收电平并产生用于控制放大级的直流电压。该直流电压被采样，并且基于有序统计技术从采样中选择最佳控制电压。传统的AGC控制环路被中断，并且所选择的控制电压被提供给放大级。

7. 发明授权

US5029182A Automatic gain control (AGC) for frequency hopping receiver 失效
标题翻译：跳频接收机的自动增益控制（AGC）
公开(公告)号：US5029182A
公开(公告)日：1991-07-02
申请号：US489867
申请日：1990-03-05
申请人： Khiem V. Cai , James L. Thomas , Patrick L. Lim
发明人： Khiem V. Cai , James L. Thomas , Patrick L. Lim
IPC分类号： H03G3/20 , H04B1/713 , H04B1/715
CPC分类号： H04B1/715 , H03G3/3068 , H04B1/713 , H04B2001/7152
摘要： The invention is an Automatic Gain Control ("AGC") sampling structure for use with frequency-hopped high frequency waveforms containing known transmitted signals embedded within communications traffic. The sampling structure is a digital structure and an AGC selection algorithm used in conjunction with a standard closed loop analog AGC circuit in which the AGC generator detects the received audio level and generates a direct current control voltage for controlling an amplification stage. This AGC control voltage is sampled during the reception of known transmitted signals to provide a series of independent AGC samples to a digital controller. The digital controller determines th eoptimum AGC control voltage based on a selection algorithm which uses the technique of ordered statistics to select the correct ordered sample to provide the optimum AGC control level for the receiver. The standard AGC control loop is the interrupted and the optimum AGC voltage selected by the digital controller is coupled to provide the direct current control voltage to the amplification stage.
摘要翻译：本发明是一种自动增益控制（“AGC”）采样结构，用于包含嵌入在通信业务中的已知传输信号的跳频高频波形。采样结构是与标准闭环模拟AGC电路一起使用的数字结构和AGC选择算法，其中AGC发生器检测接收的音频电平并产生用于控制放大级的直流控制电压。在接收已知的发射信号期间对该AGC控制电压进行采样，以向数字控制器提供一系列独立的AGC采样。数字控制器基于选择算法确定最佳AGC控制电压，该选择算法使用有序统计技术来选择正确的有序样本，为接收机提供最佳的AGC控制电平。标准的AGC控制环路被中断，由数字控制器选择的最佳AGC电压被耦合以向放大级提供直流控制电压。

8. 发明申请

US20100020900A1 DIGITAL PRE-DISTORTION TECHNIQUE USING NONLINEAR FILTERS 有权
标题翻译：使用非线性滤波器的数字预失真技术
公开(公告)号：US20100020900A1
公开(公告)日：2010-01-28
申请号：US12574796
申请日：2009-10-07
申请人： Khiem V. Cai , David B. Rutan , Matthew S. Gorder , Don C. Devendorf
发明人： Khiem V. Cai , David B. Rutan , Matthew S. Gorder , Don C. Devendorf
IPC分类号： H04L25/49
CPC分类号： H04L25/03885 , H03F1/3247 , H03F1/3276 , H04L25/49 , H04L27/2626 , H04L27/368
摘要： A method and computer program product for operating a linearizer for a circuit, including generating a set of coefficients via a characterizer; predistorting a signal input to the circuit responsive to the coefficients and generating a linearized output in response thereto; filtering the signal through a linear digital filter having linear digital filter taps, each tap other than a first tap being successively delayed by one delay unit; generating powers of the signal; inputting the generated powers of the signal through tapped delay lines, each line having nonlinear digital filter taps, each tap other than a first tap being successively delayed by one delay unit; applying the coefficients to the linear and nonlinear digital filter taps; summing each of the nonlinear digital filter taps corresponding to a certain number of delay units; and adding the sum of each of the delay units to a particular linear digital filter tap.
摘要翻译：一种用于操作电路的线性化器的方法和计算机程序产品，包括经由表征器生成一组系数; 响应于系数预失真输入到电路的信号并响应于此产生线性化的输出; 通过具有线性数字滤波器抽头的线性数字滤波器对信号进行滤波，除了连续延迟一个延迟单元的第一抽头以外的每个抽头; 产生信号的功率; 通过抽头延迟线输入信号的发生功率，每行具有非线性数字滤波器抽头，每个抽头不同于连续延迟一个延迟单元的第一抽头; 将系数应用于线性和非线性数字滤波器抽头; 对与一定数量的延迟单元相对应的每个非线性数字滤波器抽头相加; 并将每个延迟单元的和加到特定的线性数字滤波器抽头上。

9. 发明申请

US20080260066A1 Dynamic digital pre-distortion system 有权
标题翻译：动态数字预失真系统
公开(公告)号：US20080260066A1
公开(公告)日：2008-10-23
申请号：US11788451
申请日：2007-04-20
申请人： Khiem V. Cai , David B. Rutan , Ahmad Khanifar , Armando C. Cova
发明人： Khiem V. Cai , David B. Rutan , Ahmad Khanifar , Armando C. Cova
IPC分类号： H04L25/49
CPC分类号： H04B1/62 , H03F1/3241 , H03F1/3247 , H03F1/3294 , H03F3/24 , H03F2200/336 , H03F2200/451 , H03F2201/3224 , H04B1/0475 , H04B17/13 , H04B2001/0425 , H04W52/52
摘要： A Dynamic Digital Pre-Distortion (DDPD) system is disclosed to rapidly correct power amplifier (PA) non-linearity and memory effects. To perform pre-distortion, a DDPD engine predistorts an input signal in order to cancel PA nonlinearities as the signal is amplified by the PA. The DDPD engine is implemented as a composite of one linear filter and N-1 high order term linear filters. The bank of linear filters have programmable complex coefficients. To compute the coefficients, samples from the transmit path and a feedback path are captured, and covariance matrices A and B are computed using optimized hardware. After the covariance matrices are computed, Gaussian elimination processing may be employed to compute the coefficients. Mathematical and hardware optimizations may be employed to simplify and reduce the number of multiplication operands and other operations, which can enable the DDPD system to fit within a single chip.
摘要翻译：公开了动态数字预失真（DDPD）系统来快速校正功率放大器（PA）的非线性和记忆效应。为了执行预失真，DDPD引擎预失真输入信号，以便随着信号被PA放大而取消PA非线性。 DDPD引擎实现为一个线性滤波器和N-1个高阶项线性滤波器的组合。线性滤波器组具有可编程的复系数。为了计算系数，捕获来自发射路径和反馈路径的样本，并使用优化的硬件来计算协方差矩阵A和B. 在协方差矩阵被计算之后，可以采用高斯消去处理来计算系数。可以采用数学和硬件优化来简化和减少乘法操作数和其他操作的数量，这可以使DDPD系统适合于单个芯片内。

10. 发明授权

US07187735B2 Mixed technology MEMS/SiGe BiCMOS digitalized analog front end with direct RF sampling 有权
标题翻译：混合技术MEMS / SiGe BiCMOS数字化模拟前端采用直接RF采样
公开(公告)号：US07187735B2
公开(公告)日：2007-03-06
申请号：US10352407
申请日：2003-01-28
申请人： Samuel D. Kent, III , Lloyd F. Linder , Khiem V. Cai
发明人： Samuel D. Kent, III , Lloyd F. Linder , Khiem V. Cai
IPC分类号： H03H9/00 , H04B1/10
CPC分类号： H04B1/0007 , G01S19/21 , H01H1/0036 , H04B1/0003 , H04B1/1036 , H04B1/109 , H04K3/228 , H04K3/90
摘要： A digitizing analog front end (DAFE) using mixed technology on a single substrate is described. SiGe BiCMOS technology is implemented for the semiconductor components, which include a low noise amplifier and an analog-to-digital converter. Micro Electro Mechanical System (MEMS) switches are used to change the filtering characteristics of several filters, including an anti-aliasing filter and a pre-select and anti-jamming filter.
摘要翻译：描述了在单个基板上使用混合技术的数字化模拟前端（DAFE）。 SiGe BiCMOS技术适用于包括低噪声放大器和模数转换器的半导体元件。微机电系统（MEMS）开关用于改变多个滤波器的滤波特性，包括抗混叠滤波器和预选择和抗干扰滤波器。

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