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1. 发明授权

US08769382B1 Optimizing error floor performance of finite-precision layered decoders of low-density parity-check (LDPC) codes 有权
标题翻译：优化低密度奇偶校验（LDPC）码的有限精密分层解码器的误码性能
公开(公告)号：US08769382B1
公开(公告)日：2014-07-01
申请号：US13610438
申请日：2012-09-11
申请人： Nedeljko Varnica , Gregory Burd , Kiran Gunnam
发明人： Nedeljko Varnica , Gregory Burd , Kiran Gunnam
IPC分类号： H03M13/00
CPC分类号： G06F11/073 , H03M13/1102 , H03M13/1114 , H03M13/1117 , H03M13/114 , H03M13/116 , H03M13/6577 , H03M13/6591
摘要： Systems and methods are provided for selecting precisions during iterative decoding with a low-density parity check (LDPC) decoder in order to maximize LDPC code's performance in the error floor region. The selection of the precision of the messages may be done in such a way as to avoid catastrophic errors and to minimize the number of near-codeword errors during the decoding process. Another system and method to avoid catastrophic errors in the layered (serial) LDPC decoder is provided. Lastly, a system and method that select precisions and provide circuitry that optimizes the exchange of information between a soft-input, soft-output (SISO) channel detector and an error correction code (ECC) decoder for channels with memory is provided.
摘要翻译：提供了用于在利用低密度奇偶校验（LDPC）解码器的迭代解码期间选择精度的系统和方法，以便最大化LDPC码在错误楼层区域的性能。消息的精确度的选择可以以避免灾难性错误并且在解码过程期间最小化近似码字错误的数量的方式来完成。提供了在分层（串行）LDPC解码器中避免灾难性错误的另一种系统和方法。最后，提供了一种系统和方法，其提供优化软输入，软输出（SISO）信道检测器和用于具有存储器的信道的纠错码（ECC）解码器）之间的信息交换的精度和提供电路。

2. 发明授权

US08677209B2 Subwords coding using different encoding/decoding matrices 有权
标题翻译：使用不同编码/解码矩阵的子字编码
公开(公告)号：US08677209B2
公开(公告)日：2014-03-18
申请号：US12644622
申请日：2009-12-22
申请人： Kiran Gunnam , Yang Han , Shaohua Yang , Changyou Xu
发明人： Kiran Gunnam , Yang Han , Shaohua Yang , Changyou Xu
IPC分类号： H03M13/00
CPC分类号： H03M13/2957 , H03M13/1102 , H03M13/116 , H03M13/27 , H03M13/2757 , H03M13/6331 , H03M13/6343 , H04L1/0041 , H04L1/0057 , H04L1/0071
摘要： In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding subword encoders/decoders in the different subword-processing paths perform subword encoding/decoding with different encoder/decoder matrices.
摘要翻译：在将用户数据字分解为多个子字以在不同的子处理路径内进行编码和解码的通信系统中，可以通过在不同的子字处理路径中具有对应的子字编码器/解码器来增加外部码字中的位错误之间的最小距离，处理路径使用不同的编码器/解码器矩阵执行子字编码/解码。

3. 发明授权

US08527831B2 Systems and methods for low density parity check data decoding 有权
标题翻译：用于低密度奇偶校验数据解码的系统和方法
公开(公告)号：US08527831B2
公开(公告)日：2013-09-03
申请号：US12767757
申请日：2010-04-26
申请人： Zongwang Li , Kiran Gunnam , Shaohua Yang , Johnson Yen
发明人： Zongwang Li , Kiran Gunnam , Shaohua Yang , Johnson Yen
IPC分类号： G06F11/00
CPC分类号： G11B20/1833 , G11B2020/185 , G11B2220/2516 , H03M13/1122 , H03M13/3707 , H03M13/616 , H03M13/658 , H03M13/6583
摘要： Various embodiments of the present invention provide systems and methods for decoding data. As an example, a data processing circuit is disclosed that includes a multi-tier decoding circuit having a first tier decoding circuit operable to decode portions of an encoded data set exhibiting low row weight, and a second tier decoding circuit operable to decode portions of an encoded data set exhibiting high row weight.
摘要翻译：本发明的各种实施例提供了用于解码数据的系统和方法。作为示例，公开了一种数据处理电路，其包括具有第一层解码电路的多层解码电路，该第一层解码电路可操作以解码呈现低行权重的编码数据集的部分;以及第二层解码电路，其可操作以解码部分具有较高行重量的编码数据集。

4. 发明授权

US08448039B2 Error-floor mitigation of LDPC codes using targeted bit adjustments 有权
标题翻译：使用目标位调整进行LDPC码的误差降低
公开(公告)号：US08448039B2
公开(公告)日：2013-05-21
申请号：US12401116
申请日：2009-03-10
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： Embodiments of the present invention are methods for breaking one or more trapping sets in a near codeword of a failed graph-based decoder, e.g., an LDPC decoder. The methods determine, from among all bit nodes associated with one or more unsatisfied check nodes in the near codeword, which bit nodes, i.e., the suspicious bit nodes or SBNs, are most likely to be erroneous bit nodes. The methods then perform a trial in which the values of one or more SBNs are altered and decoding is re-performed. If the trial does not converge on the decoded correct codeword (DCCW), then other trials are performed until either (i) the decoder converges on the DCCW or (ii) all permitted combinations of SBNs are exhausted. The starting state of a particular trial, and the set of SBNs available to that trial may change depending on the results of previous trials.
摘要翻译：本发明的实施例是用于破坏基于失败的图形解码器（例如LDPC解码器）的近码字中的一个或多个陷印集的方法。这些方法从与近码字中的一个或多个不满足的校验节点相关联的所有比特节点中确定哪些比特节点，即可疑比特节点或SBN最可能是错误的比特节点。然后，该方法进行一次试验，其中一个或多个SBN的值被改变并且重新执行解码。如果试验没有收敛于解码的正确码字（DCCW），则执行其他试验，直到（i）解码器收敛于DCCW或（ii）所有允许的SBN组合被用尽。特定试验的起始状态以及可用于该试验的一组SBN可能会根据以前试验的结果而有所不同。

5. 发明授权

US08402324B2 Communications system employing local and global interleaving/de-interleaving 失效
标题翻译：采用本地和全局交织/解交织的通信系统
公开(公告)号：US08402324B2
公开(公告)日：2013-03-19
申请号：US12891161
申请日：2010-09-27
申请人： Kiran Gunnam , Yang Han
发明人： Kiran Gunnam , Yang Han
IPC分类号： G06F11/00
CPC分类号： H04L25/03171 , H03M13/09 , H03M13/1137 , H03M13/116 , H03M13/2732 , H03M13/2792 , H03M13/2796 , H03M13/41 , H03M13/6331 , H03M13/6561 , H03M13/6566 , H04L1/0045 , H04L1/0057 , H04L1/0071
摘要： In one embodiment, a communications system has a write path and a read path. In the write path, a local/global interleaver interleaves a user data stream, and an error-correction (EC) encoder encodes the user data stream to generate an EC codeword. A local/global de-interleaver de-interleaves the parity bits of the EC codeword, and both the original un-interleaved user data and the de-interleaved parity bits are transmitted via a noisy channel. In the read path, a channel detector recovers channel soft-output values corresponding to the codeword. A local/global interleaver interleaves the channel values, and an EC decoder decodes the interleaved values to recover the original codeword generated in the write path. A de-multiplexer de-multiplexes the user data from the parity bits. Then, a local/global de-interleaver de-interleaves the user data to obtain the original sequence of user data that was originally received at the write path.
摘要翻译：在一个实施例中，通信系统具有写入路径和读取路径。在写入路径中，本地/全局交织器交织用户数据流，并且纠错（EC）编码器对用户数据流进行编码以生成EC码字。本地/全局解交织器对EC码字的奇偶校验位进行解交织，并且经由噪声信道发送原始未交织的用户数据和去交织的奇偶校验位。在读取路径中，信道检测器恢复对应于码字的信道软输出值。本地/全局交织器对信道值进行交织，并且EC解码器解码交织值以恢复在写入路径中生成的原始码字。解复用器从奇偶校验位解复用用户数据。然后，本地/全局解交织器对用户数据进行解交织以获得最初在写入路径处接收的用户数据的原始序列。

6. 发明授权

US08381074B1 Systems and methods for utilizing a centralized queue based data processing circuit 有权
标题翻译：利用基于集中式队列的数据处理电路的系统和方法
公开(公告)号：US08381074B1
公开(公告)日：2013-02-19
申请号：US12785418
申请日：2010-05-21
申请人： Kiran Gunnam , Shaohua Yang
发明人： Kiran Gunnam , Shaohua Yang
IPC分类号： G11C29/00
CPC分类号： H03M13/27 , G06F11/1008 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/2957 , H03M13/356 , H03M13/3905 , H03M13/4138 , H03M13/6325 , H03M13/6331 , H03M13/6508
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes: providing a data detection circuit including a first detection processing circuit, a second detection processing circuit, a decoder processing circuit, and a memory circuit; performing a data detection algorithm on an input data set by the first detection processing circuit to yield a first detected output; writing a derivative of the first detected output to the memory circuit; accessing the derivative of the first detected output from the memory circuit; performing a decoder algorithm on the derivative of the first detected output using the decoder processing circuit to yield a decoded output; writing the decoded output to the memory circuit; accessing the decoded output from the memory circuit; and performing the data detection algorithm on a combination of the input data set and the decoded output to yield a second detected output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种用于数据处理的方法，包括：提供包括第一检测处理电路，第二检测处理电路，解码器处理电路和存储电路的数据检测电路; 对由第一检测处理电路设置的输入数据执行数据检测算法以产生第一检测输出; 将第一检测输出的导数写入存储器电路; 访问来自存储器电路的第一检测输出的导数; 使用解码器处理电路对第一检测输出的导数执行解码器算法以产生解码输出; 将解码的输出写入存储器电路; 从存储器电路访问解码的输出; 以及在输入数据组和解码输出的组合上执行数据检测算法以产生第二检测输出。

7. 发明授权

US08065598B1 Low latency programmable encoder with outer systematic code and low-density parity-check code 有权
标题翻译：具有外部系统代码和低密度奇偶校验码的低延迟可编程编码器
公开(公告)号：US08065598B1
公开(公告)日：2011-11-22
申请号：US12024720
申请日：2008-02-01
申请人： Kiran Gunnam , Farshid Rafiee Rad
发明人： Kiran Gunnam , Farshid Rafiee Rad
IPC分类号： G06F11/00
CPC分类号： H03M13/116 , H03M13/152 , H03M13/2906 , H03M13/611 , H03M13/6561
摘要： Low-latency programmable encoders, and more particularly, low-latency programmable encoders which use low-density parity check (LDPC) codes in combination with an outer systematic code. The LDPC encoder is programmable for any irregular circulant-based LDPC code. The code profile, block length, number of block rows, and number of block columns can vary. The LDPC encoding and the outer systematic code encoding can proceed in a parallel manner (e.g., simultaneously) instead of in a serial manner.
摘要翻译：低延迟可编程编码器，更具体地说，低延迟可编程编码器，它们结合外部系统代码使用低密度奇偶校验（LDPC）码。 LDPC编码器可编程为任何不规则的基于循环的LDPC码。代码配置文件，块长度，块行数和块列数可以有所不同。 LDPC编码和外部系统码编码可以以并行方式（例如同时进行）而不是以串行方式进行。

8. 发明申请

US20110264980A1 Systems and Methods for Low Density Parity Check Data Decoding 有权
标题翻译：低密度奇偶校验数据解码系统与方法
公开(公告)号：US20110264980A1
公开(公告)日：2011-10-27
申请号：US12767757
申请日：2010-04-26
申请人： Zongwang Li , Kiran Gunnam , Shaohua Yang , Johnson Yen
发明人： Zongwang Li , Kiran Gunnam , Shaohua Yang , Johnson Yen
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11B20/1833 , G11B2020/185 , G11B2220/2516 , H03M13/1122 , H03M13/3707 , H03M13/616 , H03M13/658 , H03M13/6583
摘要： Various embodiments of the present invention provide systems and methods for decoding data. As an example, a data processing circuit is disclosed that includes a multi-tier decoding circuit having a first tier decoding circuit operable to decode portions of an encoded data set exhibiting low row weight, and a second tier decoding circuit operable to decode portions of an encoded data set exhibiting high row weight.
摘要翻译：本发明的各种实施例提供了用于解码数据的系统和方法。作为示例，公开了一种数据处理电路，其包括具有第一层解码电路的多层解码电路，该第一层解码电路可操作以解码呈现低行权重的编码数据集的部分;以及第二层解码电路，其可操作以解码部分具有较高行重量的编码数据集。

9. 发明申请

US20110264979A1 ERROR-CORRECTION DECODER EMPLOYING EXTRINSIC MESSAGE AVERAGING 有权
标题翻译：错误修正解码器使用超级消息平均
公开(公告)号：US20110264979A1
公开(公告)日：2011-10-27
申请号：US12766038
申请日：2010-04-23
申请人： Kiran Gunnam , Shaohua Yang , Changyou Xu
发明人： Kiran Gunnam , Shaohua Yang , Changyou Xu
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/116 , H03M13/09 , H03M13/1128 , H03M13/1137 , H03M13/114 , H03M13/1142 , H03M13/2906 , H03M13/6306
摘要： In one embodiment, an LDPC decoder has a controller and an extrinsic log-likelihood (LLR) value generator. The extrinsic LLR value generator is selectively configurable to operate in either (i) a non-averaging mode that updates extrinsic LLR values without averaging or (ii) an averaging mode that updates extrinsic LLR values using averaging. Initially, the extrinsic LLR value generator is configured to generate non-averaged extrinsic LLR values, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged extrinsic LLR values. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) the extrinsic LLR value generator is configured to generate average extrinsic LLR values, and (iii) the decoder attempts to recover the correct codeword using the average extrinsic LLR values. Averaging the extrinsic LLR values may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.
摘要翻译：在一个实施例中，LDPC解码器具有控制器和外在对数似然（LLR）值发生器。外部LLR值发生器可选择性地配置为以下操作：（i）不平均更新外在LLR值的非平均模式，或（ii）使用平均更新外在LLR值的平均模式。最初，外部LLR值发生器被配置为产生非平均的外在LLR值，并且解码器尝试使用非平均的外在LLR值来恢复LDPC编码码字。如果解码器不能恢复正确的码字，则（i）控制器选择平均模式，（ii）外部LLR值发生器被配置为产生平均外在LLR值，以及（iii）解码器尝试恢复正确的码字码字使用平均外在LLR值。平衡外部LLR值可能会减慢导致解码器收敛的错误消息的传播。

10. 发明申请

US20110119553A1 SUBWORDS CODING USING DIFFERENT ENCODING/DECODING MATRICES 有权
标题翻译：使用不同的编码/解码矩阵进行子代码编码
公开(公告)号：US20110119553A1
公开(公告)日：2011-05-19
申请号：US12644622
申请日：2009-12-22
申请人： Kiran Gunnam , Yang Han , Shaohua Yang , Changyou Xu
发明人： Kiran Gunnam , Yang Han , Shaohua Yang , Changyou Xu
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2957 , H03M13/1102 , H03M13/116 , H03M13/27 , H03M13/2757 , H03M13/6331 , H03M13/6343 , H04L1/0041 , H04L1/0057 , H04L1/0071
摘要： In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding subword encoders/decoders in the different subword-processing paths perform subword encoding/decoding with different encoder/decoder matrices.
摘要翻译：在将用户数据字分解为多个子字以在不同的子处理路径内进行编码和解码的通信系统中，可以通过在不同的子字处理路径中具有对应的子字编码器/解码器来增加外部码字中的位错误之间的最小距离，处理路径使用不同的编码器/解码器矩阵执行子字编码/解码。

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