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    • 3. 发明授权
    • Method and apparatus for a parameterized interleaver design process
    • 用于参数化交织器设计过程的方法和装置
    • US08527833B2
    • 2013-09-03
    • US13231474
    • 2011-09-13
    • Rohit SeshadriMustafa ErozLin-Nan Lee
    • Rohit SeshadriMustafa ErozLin-Nan Lee
    • H03M13/00
    • H03M13/2767H03M13/275H03M13/276H03M13/2789
    • A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations.
    • 提供了一种参数化的交织器设计过程,其优化了任何尺寸的交织器的设计,并且可以仅使用少量设计参数来完全指定。 根据参数化交织器设计处理,生成长度为N的交织器pi(i)。 定义了多个子鉴别掩码,并且将第一中间交织器置换分割成多个子组,其中子组的数量对应于子鉴别掩码的数量。 第一中间交织器排列的每个子组被划分成多个其他子组,并且每个子质量掩模被应用于第一中间交织器排列的相应子组的其他子组中的每一个,导致相应部分 第二中间交织器排列。 至少部分地基于第一和第二中间交织器排列来生成所产生的交织器pi(i)。
    • 4. 发明授权
    • Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels
    • 用于多输入多输出通道的低密度奇偶校验码的代码设计和实现改进
    • US08392793B2
    • 2013-03-05
    • US12753528
    • 2010-04-02
    • Mustafa ErozLin-Nan LeeFeng-Wen Sun
    • Mustafa ErozLin-Nan LeeFeng-Wen Sun
    • H03M13/00
    • H03M13/1185H03M13/1137H03M13/152H03M13/2906H04B7/02H04L1/005H04L1/0057H04L1/0625
    • Methods include configuring M parallel accumulation engines, accumulating a first information bit at a first set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the first set of specific parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the second set of specific parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted. Related systems are described.
    • 方法包括配置M并行累积引擎,使用累积引擎在第一组特定奇偶校验位地址处累积第一信息位,将第一组特定奇偶校验位地址的每个成员的奇偶校验位地址增加预定的偏移量 对于每个新的信息位,在与特定奇偶校验位地址相偏移的奇偶校验位地址处累积后续信息比特,直到达到M + 1个信息比特为止,将下一个M个信息比特累加在第二组 使用累积引擎的特定奇偶校验位地址,增加第二组特定奇偶校验位地址的每个成员的奇偶校验位地址每个新信息比特的预定偏移量; 并重复累积和增加地址直到信息位耗尽。 描述相关系统。