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1. 发明授权

US06971098B2 Method and apparatus for managing transaction requests in a multi-node architecture 失效
标题翻译：用于管理多节点架构中的事务请求的方法和装置
公开(公告)号：US06971098B2
公开(公告)日：2005-11-29
申请号：US09891522
申请日：2001-06-27
申请人： Manoj Khare , Akhilesh Kumar , Ioannis Schoinas , Lily Pao Looi
发明人： Manoj Khare , Akhilesh Kumar , Ioannis Schoinas , Lily Pao Looi
IPC分类号： G06F9/46 , G06F9/54 , G06F15/163
CPC分类号： G06F9/52 , G06F12/0833
摘要： Embodiments of the present invention relate to methods and apparatus for managing transaction requests in a multi-node architecture. In one embodiment, a previously received ordered group request may be forwarded to a destination agent. Whether a next received ordered group request belongs to a same ordered group as the previously received ordered group request may be determined. Additionally, it may be determined whether an ordering fork is encountered if the next received ordered group request belongs to the same ordered group as the previously received ordered group request. If an ordering fork is encountered, it may be determined whether a request complete message for the previously received ordered group request has been received. If the request complete message for the previously received ordered group request has not been received and the next received ordered group request in the same ordered group is at least one of a un-ordered request and a forward-ordered request, then the next received ordered group request may be forwarded to the destination agent after the request complete message for the previously received at least one of a forward-ordered request and a sequential-ordered request issued on a different path at the ordering fork has been received.
摘要翻译：本发明的实施例涉及用于在多节点架构中管理事务请求的方法和装置。在一个实施例中，先前接收到的有序组请求可以被转发到目的地代理。可以确定下一个接收到的有序组请求是否属于与先前接收的有序组请求相同的有序组。此外，如果下一个接收到的有序组请求属于与先前接收的有序组请求相同的有序组，则可以确定是否遇到排序分支。如果遇到订货叉，则可以确定是否已经接收到先前接收到的订购组请求的请求完成消息。如果先前接收到的订购组请求的请求完成消息未被接收，并且相同有序组中的下一个接收到的有序组请求是未排序请求和转发请求中的至少一个，则下一个接收到的订单在已经接收到先前接收到的顺序请求和在订购叉上的不同路径上发布的顺序请求的请求的至少一个的请求完成消息之后，组请求可以被转发到目的地代理。

2. 发明授权

US07370135B2 Band configuration agent for link based computing system 有权
标题翻译：基于链路的计算系统的频带配置代理
公开(公告)号：US07370135B2
公开(公告)日：2008-05-06
申请号：US11284520
申请日：2005-11-21
申请人： Eric Delano , Ioannis Schoinas , Akhilesh Kumar , Doddaballapur Narasimha-Murthy Jayasimha
发明人： Eric Delano , Ioannis Schoinas , Akhilesh Kumar , Doddaballapur Narasimha-Murthy Jayasimha
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A method is described that involves directing a configuration request through a switch core to a configuration agent. The method also involves processing the configuration request at the configuration agent. The method also involves sending a configuration command derived from the configuration request from the configuration agent to the switch core. The method also involves executing the configuration command at an agent to which the configuration command pertains.
摘要翻译：描述了一种方法，其涉及通过交换机核心将配置请求定向到配置代理。该方法还涉及在配置代理处理配置请求。该方法还涉及从配置代理将配置命令从配置代理发送到交换机核心。该方法还涉及在配置命令所在的代理处执行配置命令。

3. 发明申请

US20070118678A1 Band configuration agent for link based computing system 有权
标题翻译：基于链路的计算系统的频带配置代理
公开(公告)号：US20070118678A1
公开(公告)日：2007-05-24
申请号：US11284520
申请日：2005-11-21
申请人： Eric Delano , Ioannis Schoinas , Akhilesh Kumar , Doddaballapur Jayasimha
发明人： Eric Delano , Ioannis Schoinas , Akhilesh Kumar , Doddaballapur Jayasimha
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A method is described that involves directing a configuration request through a switch core to a configuration agent. The method also involves processing the configuration request at the configuration agent. The method also involves sending a configuration command derived from the configuration request from the configuration agent to the switch core. The method also involves executing the configuration command at an agent to which the configuration command pertains.
摘要翻译：描述了一种方法，其涉及通过交换机核心将配置请求定向到配置代理。该方法还涉及在配置代理处理配置请求。该方法还涉及从配置代理将配置命令从配置代理发送到交换机核心。该方法还涉及在配置命令所在的代理处执行配置命令。

4. 发明申请

US20070150699A1 Firm partitioning in a system with a point-to-point interconnect 审中-公开
标题翻译：在具有点对点互连的系统中进行牢固的分区
公开(公告)号：US20070150699A1
公开(公告)日：2007-06-28
申请号：US11321213
申请日：2005-12-28
申请人： Ioannis Schoinas , Doddaballapur Jayasimha , Eric Delano , Allen Baum , Akhilesh Kumar , Steven Chang , Suresh Chittor , Kenneth Creta , Stephen Van Doren
发明人： Ioannis Schoinas , Doddaballapur Jayasimha , Eric Delano , Allen Baum , Akhilesh Kumar , Steven Chang , Suresh Chittor , Kenneth Creta , Stephen Van Doren
IPC分类号： G06F15/00
CPC分类号： H04L45/00 , H04L45/04
摘要： Methods and apparatuses for firm partitioning of a computing platform.
摘要翻译：用于计算平台的固定分区的方法和装置。

5. 发明申请

US20060184480A1 Method, system, and apparatus for dynamic reconfiguration of resources 有权
公开(公告)号：US20060184480A1
公开(公告)日：2006-08-17
申请号：US11011300
申请日：2004-12-13
申请人： Mani Ayyar , Eric Delano , Ioannis Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose Vargas
IPC分类号： G06N5/00
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

6. 发明申请

US20090254712A1 ADAPTIVE CACHE ORGANIZATION FOR CHIP MULTIPROCESSORS 审中-公开
标题翻译：自适应高速缓存组织用于芯片多重处理器
公开(公告)号：US20090254712A1
公开(公告)日：2009-10-08
申请号：US12061027
申请日：2008-04-02
申请人： Naveen Cherukuri , Ioannis Schoinas , Akhilesh Kumar , Seungjoon Park , Ching-Tsun Chou
发明人： Naveen Cherukuri , Ioannis Schoinas , Akhilesh Kumar , Seungjoon Park , Ching-Tsun Chou
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/084 , G06F2212/271
摘要： A method, chip multiprocessor tile, and a chip multiprocessor with amorphous caching are disclosed. An initial processing core 404 may retrieve a data block from a data storage. An initial amorphous cache bank 410 adjacent to the initial processing core 404 may store an initial data block copy 422. A home bank directory 424 may register the initial data block copy 422.
摘要翻译：公开了一种方法，芯片多处理器瓦片和具有非晶缓存的芯片多处理器。初始处理核心404可以从数据存储器检索数据块。与初始处理核心404相邻的初始非晶缓存组410可以存储初始数据块副本422.归属库目录424可以注册初始数据块拷贝422。

7. 发明授权

US07433985B2 Conditional and vectored system management interrupts 有权
标题翻译：有条件和向量的系统管理中断
公开(公告)号：US07433985B2
公开(公告)日：2008-10-07
申请号：US11320923
申请日：2005-12-28
申请人： Mani Ayyar , Ioannis Schoinas , Rama R. Menon , Aniruddha Vaidya , Akhilesh Kumar
发明人： Mani Ayyar , Ioannis Schoinas , Rama R. Menon , Aniruddha Vaidya , Akhilesh Kumar
IPC分类号： G06F13/24 , G06F13/26 , G06F13/32
CPC分类号： G06F13/24
摘要： An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.
摘要翻译：本发明的一个实施例是一种处理系统管理中断的技术。系统管理中断（SMI）被接收。 SMI与系统管理模式（SMM）相关联。至少处理器广播条件SMI处理器间中断（IPI）消息。在不等待至少处理器检查SMM的情况下处理SMI。在SMI处理结束时将清除待处理的SMI广播到处理器，以清除待处理的SMI条件。

8. 发明申请

US20070150632A1 Conditional and vectored system management interrupts 有权
标题翻译：有条件和向量的系统管理中断
公开(公告)号：US20070150632A1
公开(公告)日：2007-06-28
申请号：US11320923
申请日：2005-12-28
申请人： Mani Ayyar , Ioannis Schoinas , Rama Menon , Aniruddha Vaidya , Akhilesh Kumar
发明人： Mani Ayyar , Ioannis Schoinas , Rama Menon , Aniruddha Vaidya , Akhilesh Kumar
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.
摘要翻译：本发明的一个实施例是一种处理系统管理中断的技术。系统管理中断（SMI）被接收。 SMI与系统管理模式（SMM）相关联。至少处理器广播条件SMI处理器间中断（IPI）消息。在不等待至少处理器检查SMM的情况下处理SMI。在SMI处理结束时将清除待处理的SMI广播到处理器，以清除待处理的SMI条件。

9. 发明申请

US20050204193A1 Dynamic interconnect width reduction to improve interconnect availability 有权
标题翻译：动态互连宽度减少，以提高互连可用性
公开(公告)号：US20050204193A1
公开(公告)日：2005-09-15
申请号：US10801448
申请日：2004-03-12
申请人： Phanindra Mannava , Victor Lee , Akhilesh Kumar , Doddaballapur Jayasimha , Ioannis Schoinas
发明人： Phanindra Mannava , Victor Lee , Akhilesh Kumar , Doddaballapur Jayasimha , Ioannis Schoinas
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/1443 , G06F11/2007 , G06F2213/0038 , H04L1/1867 , H04L2001/0094
摘要： In some embodiments an apparatus includes a transmission error detector to detect an error of a transmission of an interconnect and a transmitting agent to retry the transmission in response to the detected error. The apparatus also includes a hard failure detector to detect a hard failure of the interconnect if the retry is unsuccessful, and a transmission width reducer to reduce a transmission width of the interconnect in response to the hard failure detector. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，一种装置包括传输错误检测器，用于响应于检测到的错误来检测互连的传输错误和发送代理重试传输。如果重试不成功，该装置还包括硬故障检测器，用于检测互连的硬故障;以及传输宽度减小器，以响应于硬故障检测器来减小互连的传输宽度。描述和要求保护其他实施例。

10. 发明申请

US20060106993A1 Mechanism for handling explicit writeback in a cache coherent multi-node architecture 审中-公开
公开(公告)号：US20060106993A1
公开(公告)日：2006-05-18
申请号：US11321632
申请日：2005-12-28
申请人： Manoj Khare , Lily Looi , Akhilesh Kumar
发明人： Manoj Khare , Lily Looi , Akhilesh Kumar
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0804 , G06F12/0828
摘要： A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

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