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1. 发明授权

US06971098B2 Method and apparatus for managing transaction requests in a multi-node architecture 失效
标题翻译：用于管理多节点架构中的事务请求的方法和装置
公开(公告)号：US06971098B2
公开(公告)日：2005-11-29
申请号：US09891522
申请日：2001-06-27
申请人： Manoj Khare , Akhilesh Kumar , Ioannis Schoinas , Lily Pao Looi
发明人： Manoj Khare , Akhilesh Kumar , Ioannis Schoinas , Lily Pao Looi
IPC分类号： G06F9/46 , G06F9/54 , G06F15/163
CPC分类号： G06F9/52 , G06F12/0833
摘要： Embodiments of the present invention relate to methods and apparatus for managing transaction requests in a multi-node architecture. In one embodiment, a previously received ordered group request may be forwarded to a destination agent. Whether a next received ordered group request belongs to a same ordered group as the previously received ordered group request may be determined. Additionally, it may be determined whether an ordering fork is encountered if the next received ordered group request belongs to the same ordered group as the previously received ordered group request. If an ordering fork is encountered, it may be determined whether a request complete message for the previously received ordered group request has been received. If the request complete message for the previously received ordered group request has not been received and the next received ordered group request in the same ordered group is at least one of a un-ordered request and a forward-ordered request, then the next received ordered group request may be forwarded to the destination agent after the request complete message for the previously received at least one of a forward-ordered request and a sequential-ordered request issued on a different path at the ordering fork has been received.
摘要翻译：本发明的实施例涉及用于在多节点架构中管理事务请求的方法和装置。在一个实施例中，先前接收到的有序组请求可以被转发到目的地代理。可以确定下一个接收到的有序组请求是否属于与先前接收的有序组请求相同的有序组。此外，如果下一个接收到的有序组请求属于与先前接收的有序组请求相同的有序组，则可以确定是否遇到排序分支。如果遇到订货叉，则可以确定是否已经接收到先前接收到的订购组请求的请求完成消息。如果先前接收到的订购组请求的请求完成消息未被接收，并且相同有序组中的下一个接收到的有序组请求是未排序请求和转发请求中的至少一个，则下一个接收到的订单在已经接收到先前接收到的顺序请求和在订购叉上的不同路径上发布的顺序请求的请求的至少一个的请求完成消息之后，组请求可以被转发到目的地代理。

2. 发明授权

US06810467B1 Method and apparatus for centralized snoop filtering 有权
标题翻译：用于集中侦听过滤的方法和装置
公开(公告)号：US06810467B1
公开(公告)日：2004-10-26
申请号：US09643382
申请日：2000-08-21
申请人： Manoj Khare , Faye A. Briggs , Kai Cheng , Lily Pao Looi
发明人： Manoj Khare , Faye A. Briggs , Kai Cheng , Lily Pao Looi
IPC分类号： G06F1208
CPC分类号： G06F12/0831 , G06F12/0822 , G06F12/0828 , G06F2212/507
摘要： An example embodiment of a computer system utilizing a central snoop filter includes several nodes coupled together via a switching device. Each of the nodes may include several processors and caches as well as a block of system memory. All traffic from one node to another takes place through the switching device. The switching device includes a snoop filter that tracks cache line coherency information for all caches in the computer system. The snoop filter has enough entries to track the tags and state information for all entries in all caches in all of the system's nodes. In addition to the tag and state information, the snoop filter stores information indicating which of the nodes has a copy of each cache line. The snoop filter serves in part to keep snoop transactions from being performed at nodes that do not contain a copy of the subject cache line, thereby reducing system overhead, reducing traffic across the system interconnect busses, and reducing the amount of time required to perform snoop transactions.
摘要翻译：利用中央窥探滤波器的计算机系统的示例性实施例包括经由交换设备耦合在一起的多个节点。每个节点可以包括几个处理器和高速缓存以及系统存储器块。从一个节点到另一个节点的所有业务通过交换设备进行。交换设备包括一个窥探过滤器，其跟踪计算机系统中所有高速缓存的高速缓存行一致性信息。监听过滤器具有足够的条目来跟踪所有系统节点中所有高速缓存中所有条目的标签和状态信息。除了标签和状态信息之外，窥探过滤器存储指示哪个节点具有每个高速缓存行的副本的信息。窥探过滤器部分地用于在不包含主体高速缓存行的副本的节点处执行窥探事务，从而减少系统开销，减少跨系统互连总线的流量，并减少执行窥探所需的时间量交易。

3. 发明授权

US08782456B2 Dynamic and idle power reduction sequence using recombinant clock and power gating 有权
标题翻译：使用重组时钟和电源门控的动态和空闲功率降低序列
公开(公告)号：US08782456B2
公开(公告)日：2014-07-15
申请号：US12978452
申请日：2010-12-24
申请人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
发明人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
摘要翻译：描述了使用重组时钟和/或电源门控的用于动态和/或空闲功率降低序列的方法和装置。在一个实施例中，集成输入/输出（IIO）逻辑的至少一部分是基于功率降低序列进入较低功耗状态。还公开了其他实施例。

4. 发明申请

US20110296222A1 DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK AND POWER GATING 有权
标题翻译：使用重构时钟和功率增益的动态和空闲功率降低序列
公开(公告)号：US20110296222A1
公开(公告)日：2011-12-01
申请号：US12978452
申请日：2010-12-24
申请人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
发明人： Sin S. Tan , Srikanth T. Srinivasan , Sivakumar Radhakrishnan , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/32 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
摘要翻译：描述了使用重组时钟和/或电源门控的用于动态和/或空闲功率降低序列的方法和装置。在一个实施例中，集成输入/输出（IIO）逻辑的至少一部分是基于功率降低序列进入较低功耗状态。还公开了其他实施例。

5. 发明授权

US07093079B2 Snoop filter bypass 有权
标题翻译：窥探过滤器旁路
公开(公告)号：US07093079B2
公开(公告)日：2006-08-15
申请号：US10323200
申请日：2002-12-17
申请人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
发明人： Tuan M. Quach , Lily Pao Looi , Kai Cheng
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/082
摘要： Machine-readable media, methods, and apparatus are described for processing coherent requests of a computing device comprising multiple cache nodes. In some embodiments, a coherent switch may receive from a requesting cache node a coherent request for a line of memory. The coherent switch may further issue snoop requests to one or more non-requesting cache nodes based upon whether a snoop filter bypass mode is enabled. In particular, the coherent switch when not in snoop filter bypass mode may obtain coherency data from a snoop filter and may issue snoop requests to zero or more non-requesting cache nodes based upon the coherency data obtained from the snoop filter. Further, the coherent switch when in snoop filter bypass mode may bypass the snoop filter and may issue snoop requests to all non-requesting cache agents.
摘要翻译：描述了用于处理包括多个高速缓存节点的计算设备的相干请求的机器可读介质，方法和装置。在一些实施例中，相干开关可以从请求的高速缓存节点接收对一行存储器的相干请求。基于是否启用窥探过滤器旁路模式，相干交换机可以进一步向一个或多个非请求高速缓存节点发出窥探请求。特别地，当不在窥探过滤器旁路模式时，相干开关可以从窥探过滤器获得一致性数据，并且可以基于从窥探过滤器获得的一致性数据向0个或更多个非请求缓存节点发出窥探请求。此外，在窥探过滤器旁路模式中的相干交换机可以绕过窥探过滤器并且可以向所有不请求的缓存代理发出窥探请求。

6. 发明授权

US09146610B2 Throttling integrated link 有权
标题翻译：节流综合链接
公开(公告)号：US09146610B2
公开(公告)日：2015-09-29
申请号：US13040507
申请日：2011-03-04
申请人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
发明人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32 , G06F13/42
CPC分类号： G06F13/4059 , G06F1/3206 , G06F1/3253 , G06F13/4027 , G06F13/4286 , G06F13/4295 , Y02B60/1228 , Y02B60/1235 , Y02D10/151
摘要： Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
摘要翻译：描述了用于对与处理器集成在同一裸片上的接口进行节流的方法和装置。在一个实施例中，来自集成输入/输出集线器（例如，集成在与处理器相同的芯片上）的信号引起耦合在IIO和输入/输出（IO）设备之间的链路的节流。还公开了其他实施例。

7. 发明授权

US09110666B2 Throttling integrated link 有权
公开(公告)号：US09110666B2
公开(公告)日：2015-08-18
申请号：US13040507
申请日：2011-03-04
申请人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
发明人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F1/32 , G06F13/42
摘要： Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.

8. 发明申请

US20120079159A1 Throttling Integrated Link 有权
标题翻译：节流综合链路
公开(公告)号：US20120079159A1
公开(公告)日：2012-03-29
申请号：US13040507
申请日：2011-03-04
申请人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
发明人： Ravi Rajwar , Robert A. Mayer , Stephan J. Jourdan , Lily Pao Looi
IPC分类号： G06F13/36 , G06F13/14
CPC分类号： G06F13/4059 , G06F1/3206 , G06F1/3253 , G06F13/4027 , G06F13/4286 , G06F13/4295 , Y02B60/1228 , Y02B60/1235 , Y02D10/151
摘要： Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
摘要翻译：描述了用于对与处理器集成在同一裸片上的接口进行节流的方法和装置。在一个实施例中，来自集成输入/输出集线器（例如，集成在与处理器相同的芯片上）的信号引起耦合在IIO和输入/输出（IO）设备之间的链路的节流。还公开了其他实施例。

9. 发明申请

US20110296216A1 INTEGRATION OF PROCESSOR AND INPUT/OUTPUT HUB 有权
标题翻译：处理器和输入/输出总线的集成
公开(公告)号：US20110296216A1
公开(公告)日：2011-12-01
申请号：US12791836
申请日：2010-06-01
申请人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
发明人： Lily Pao Looi , Stephan J. Jourdan , Selim Bilgin , Sin S. Tan , Anant S. Deval , Srikanth T. Srinivasan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
摘要翻译：描述了用于集成处理器和输入/输出集线器的方法和装置。在一个实施例中，边带信号可能导致处理器或集成I / O逻辑的电源管理状态的改变。单个集成电路管芯可以包括处理器和集成I / O逻辑。还公开了其他实施例。

10. 发明授权

US5930486A Method and device for gracious arbitration of access to a computer system resource 失效
标题翻译：用于访问计算机系统资源的亲和仲裁的方法和装置
公开(公告)号：US5930486A
公开(公告)日：1999-07-27
申请号：US707884
申请日：1996-09-09
申请人： Lily Pao Looi , Nitin Borkar , Frank Verhoorn
发明人： Lily Pao Looi , Nitin Borkar , Frank Verhoorn
IPC分类号： G06F13/364 , G06F13/362
CPC分类号： G06F13/364
摘要： A computer system includes a priority arbitration scheme that prevents "hogging" of a bus by a priority agent. The computer system comprises at least one agent, at least one priority agent, a system resource, and a bus coupling the agent, priority agent, and system resource to one another. An arbiter is coupled to the bus, agent, and priority agent to receive request signals from the agent and the priority agent and to grant control of the bus to one of the agent and priority agent for access to the system resource. The priority agent is granted control of the bus whenever the priority agent asserts a request signal, as soon as the bus becomes next available. The priority agent relinquishes control of the bus to the agent, for a predetermined portion of the bus bandwidth, when a request signal is asserted by the agent.
摘要翻译：计算机系统包括优先权仲裁方案，其防止优先代理人对总线进行“占用”。计算机系统包括至少一个代理，至少一个优先级代理，系统资源和将代理，优先级代理和系统资源彼此耦合的总线。仲裁器耦合到总线，代理和优先级代理以从代理和优先级代理接收请求信号，并且将总线的控制权授予代理和优先级代理之一用于访问系统资源。一旦总线变为下一个可用，优先权代理就会在优先权代理人断言一个请求信号时被控制总线。当代理人断言请求信号时，优先权代理将总线的总线放弃到总线带宽的预定部分。

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