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1. 发明申请

US20210359774A1 DETECTING A MOVING OBJECT BASED ON A PHASE OF CHANNEL IMPULSE RESPONSES 有权
公开(公告)号：US20210359774A1
公开(公告)日：2021-11-18
申请号：US16872851
申请日：2020-05-12
申请人： NXP B.V.
发明人： Stefan Tertinek , Salvatore Drago , Raf Lodewijk Jan Roovers
IPC分类号： H04B17/364 , H04L25/02
摘要： A moving object detector detects a moving object in a channel. The detection comprises the detector receiving a plurality of frames based on a transmitter transmitting a plurality of frames over a channel. One or more channel impulse responses (CIRs) of the channel is determined based on the received plurality of frames. The detector determines a CIR phase for each of the CIRs and a phase signal is formed based on a phase value of the CIR phase for each of the CIRs. The detector compares the phase signal with a target signal and detects the moving object in the channel based on the comparison.

2. 发明授权

US09571071B2 Frequency synthesizer circuit 有权
标题翻译：频率合成器电路
公开(公告)号：US09571071B2
公开(公告)日：2017-02-14
申请号：US14747143
申请日：2015-06-23
申请人： NXP B.V.
发明人： Tarik Saric , Salvatore Drago
IPC分类号： H03D3/18 , H03D3/24 , H03K3/03 , H03L7/099 , H03L7/22 , H04B1/16
CPC分类号： H03K3/0315 , H03L7/099 , H03L7/22 , H03L2207/06 , H04B1/16
摘要： The invention relates to frequency synthesizer circuits, and in particular to frequency synthesizer circuits characterized by a small channel spacing. Embodiments disclosed include a frequency synthesizer circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module; configured to delay an input reference signal to generate a delayed reference signal; and a duty cycle module configured to modulate the oscillator enable signal based on a period of an input reference signal and the delay of the delayed reference signal, such that a ratio between the output frequency and the frequency of the input reference signal is a non-integer.
摘要翻译：本发明涉及频率合成器电路，特别涉及以小信道间隔为特征的频率合成器电路。所公开的实施例包括用于无线电接收机的频率合成器电路，该电路包括：数字控制振荡器，被配置为在施加振荡器使能信号时产生具有输出频率的输出信号; 一个延迟模块; 被配置为延迟输入参考信号以产生延迟的参考信号; 以及占空比模块，被配置为基于输入参考信号的周期和延迟的参考信号的延迟来调制振荡器使能信号，使得输出频率和输入参考信号的频率之间的比率是非零的，整数。

3. 发明申请

US20150349755A1 FREQUENCY CONVERTER 有权
标题翻译：频率转换器
公开(公告)号：US20150349755A1
公开(公告)日：2015-12-03
申请号：US14702884
申请日：2015-05-04
申请人： NXP B.V.
发明人： Jan van Sinderen , Salvatore Drago
IPC分类号： H03K3/03 , H03K5/00
CPC分类号： H03K3/0315 , H03D7/125 , H03D7/165 , H03D2200/0066 , H03D2200/0074 , H03K5/00006
摘要： A frequency converter, comprising a multi-phase local oscillator and a multi-phase mixer. The mixer comprises a plurality of mixer switches, each connected to a respective amplifier. The local oscillator is configured to provide a switching signal to each mixer switch, and comprises a plurality of inverters configured as a ring oscillator.
摘要翻译：一种变频器，包括多相本地振荡器和多相混频器。该混频器包括多个混频器开关，每个混频器开关连接到相应的放大器。本地振荡器被配置为向每个混频器开关提供开关信号，并且包括被配置为环形振荡器的多个反相器。

4. 发明授权

US09509290B2 Frequency converter 有权
标题翻译：频率转换器
公开(公告)号：US09509290B2
公开(公告)日：2016-11-29
申请号：US14702884
申请日：2015-05-04
申请人： NXP B.V.
发明人： Jan van Sinderen , Salvatore Drago
IPC分类号： H03K3/03 , H03D7/12 , H03K5/00 , H03D7/16
CPC分类号： H03K3/0315 , H03D7/125 , H03D7/165 , H03D2200/0066 , H03D2200/0074 , H03K5/00006
摘要： A frequency converter, comprising a multi-phase local oscillator and a multi-phase mixer. The mixer comprises a plurality of mixer switches, each connected to a respective amplifier. The local oscillator is configured to provide a switching signal to each mixer switch, and comprises a plurality of inverters configured as a ring oscillator.
摘要翻译：一种变频器，包括多相本地振荡器和多相混频器。混频器包括多个混频器开关，每个混频器开关连接到相应的放大器。本地振荡器被配置为向每个混频器开关提供开关信号，并且包括被配置为环形振荡器的多个反相器。

5. 发明申请

US20150180496A1 PHASE ESTIMATOR 有权
标题翻译：相位估计器
公开(公告)号：US20150180496A1
公开(公告)日：2015-06-25
申请号：US14551904
申请日：2014-11-24
申请人： NXP B.V.
发明人： Salvatore Drago
IPC分类号： H03M1/08 , H03M1/12 , H03M1/18 , H03M1/00
CPC分类号： H03M1/38 , H03M1/46 , H03M1/462 , H03M1/804 , H04L27/3818
摘要： A phase estimator comprising a first input terminal configured to receive a first analogue input signal; a second input terminal configured to receive a second analogue input signal, wherein the second analogue input signal is 90° out of phase with the first analogue input signal. The phase estimator is configured to provide a digital word representative of the phase of the first analogue input signal and the second analogue input signal. The phase estimator comprises a register configured to store N bits as a digital word a first reference signal generator, a second reference signal generator and a comparator.
摘要翻译：相位估计器，包括被配置为接收第一模拟输入信号的第一输入端; 第二输入端，被配置为接收第二模拟输入信号，其中所述第二模拟输入信号与所述第一模拟输入信号相差90°。相位估计器被配置为提供表示第一模拟输入信号和第二模拟输入信号的相位的数字字。相位估计器包括被配置为将N位作为数字字存储的第一参考信号发生器，第二参考信号发生器和比较器的寄存器。

6. 发明授权

US11557910B2 Power management for applications having duty-cycled high peak supply currents 有权
公开(公告)号：US11557910B2
公开(公告)日：2023-01-17
申请号：US17131041
申请日：2020-12-22
申请人： NXP B.V.
发明人： Jan van Sinderen , Salvatore Drago , Gerard Villar Pique , Esa Petri Tarvainen , Wolfgang Hoess
IPC分类号： H02J7/00
摘要： A method for power management for applications having duty-cycled high peak supply currents includes charging a buffer capacitor with a first current supplied by a battery, wherein the first current is limited by a current limiter. A load is supplied with a second current supplied by the buffer capacitor, wherein the second current comprises a pulsed current. The current limiter is controlled with at least one of a plurality of sensor inputs to limit a capacity degradation of the battery.

7. 发明申请

US20160036385A1 FREQUENCY DOWN-CONVERSION 有权
标题翻译：频率下变频
公开(公告)号：US20160036385A1
公开(公告)日：2016-02-04
申请号：US14449556
申请日：2014-08-01
申请人： NXP B.V.
发明人： Frank Leong , Salvatore Drago
IPC分类号： H03D7/16 , H04B1/16 , H03D7/18
CPC分类号： H03D7/165 , H03D7/161 , H03D7/166 , H03D7/18 , H04B1/16
摘要： Apparatus and methods concern down-converting a radio frequency (RF) signal. As an example, one apparatus includes a first mixer and a second mixer. The first mixer down-converts an RF signal to produce a first intermediate frequency (IF) signal. The second mixer down-converts the first IF signal to produce a second IF signal having a plurality of phase components. The down-converter also includes a plurality of summing circuits. Each of the summing circuits is configured to combine various ones of the phase components of the second IF signal to produce a respective phase component of a third IF signal. The number of phase components in the third IF signal is different from the number of phase components in the second IF signal.
摘要翻译：装置和方法涉及下变频射频（RF）信号。作为示例，一个装置包括第一混合器和第二混合器。第一混频器对RF信号进行下变频以产生第一中频（IF）信号。第二混频器对第一IF信号进行下变频以产生具有多个相位分量的第二IF信号。下变换器还包括多个求和电路。每个求和电路被配置为组合第二IF信号的各个相位分量以产生第三IF信号的相应相位分量。第三IF信号中的相位分量的数量与第二IF信号中的相位分量的数量不同。

8. 发明授权

US09331634B2 Frequency down-conversion 有权
标题翻译：频率下转换
公开(公告)号：US09331634B2
公开(公告)日：2016-05-03
申请号：US14449556
申请日：2014-08-01
申请人： NXP B.V.
发明人： Frank Leong , Salvatore Drago
IPC分类号： H04B1/26 , H03D7/16 , H03D7/18 , H04B1/16
CPC分类号： H03D7/165 , H03D7/161 , H03D7/166 , H03D7/18 , H04B1/16
摘要： Apparatus and methods concern down-converting a radio frequency (RF) signal. As an example, one apparatus includes a first mixer and a second mixer. The first mixer down-converts an RF signal to produce a first intermediate frequency (IF) signal. The second mixer down-converts the first IF signal to produce a second IF signal having a plurality of phase components. The down-converter also includes a plurality of summing circuits. Each of the summing circuits is configured to combine various ones of the phase components of the second IF signal to produce a respective phase component of a third IF signal. The number of phase components in the third IF signal is different from the number of phase components in the second IF signal.
摘要翻译：装置和方法涉及下变频射频（RF）信号。作为示例，一个装置包括第一混合器和第二混合器。第一混频器对RF信号进行下变频以产生第一中频（IF）信号。第二混频器对第一IF信号进行下变频以产生具有多个相位分量的第二IF信号。下变换器还包括多个求和电路。每个求和电路被配置为组合第二IF信号的各个相位分量以产生第三IF信号的相应相位分量。第三IF信号中的相位分量的数量与第二IF信号中的相位分量的数量不同。

9. 发明申请

US20160006421A1 FREQUENCY SYNTHESISER CIRCUIT 有权
标题翻译：频率合成器电路
公开(公告)号：US20160006421A1
公开(公告)日：2016-01-07
申请号：US14747143
申请日：2015-06-23
申请人： NXP B.V.
发明人： Tarik Saric , Salvatore Drago
IPC分类号： H03K3/03 , H04B1/16
CPC分类号： H03K3/0315 , H03L7/099 , H03L7/22 , H03L2207/06 , H04B1/16
摘要： The invention relates to frequency synthesiser circuits, and in particular to frequency synthesiser circuits characterised by a small channel spacing. Embodiments disclosed include a frequency synthesiser circuit (100) for a radio receiver, the circuit comprising: a digitally controlled oscillator (118) configured to generate an output signal (128) with an output frequency on application of an oscillator enable signal (126); a delay module (160; 210) configured to delay an input reference signal (142) to generate a delayed reference signal (144; 244); and a duty cycle module (150) configured to modulate the oscillator enable signal based on a period of an input reference signal (142) and the delay of the delayed reference signal (144), such that a ratio between the output frequency and the frequency of the input reference signal (142) is a non-integer.
摘要翻译：本发明涉及频率合成器电路，特别涉及以小信道间隔为特征的频率合成器电路。所公开的实施例包括用于无线电接收机的频率合成器电路（100），该电路包括：数字控制振荡器（118），被配置为在施加振荡器使能信号（126）时产生具有输出频率的输出信号（128）。延迟模块（160; 210），被配置为延迟输入参考信号（142）以产生延迟的参考信号（144; 244）; 以及占空比模块（150），被配置为基于输入参考信号（142）的周期和延迟的参考信号（144）的延迟来调制振荡器使能信号，使得输出频率和频率之间的比率的输入参考信号（142）是非整数。

10. 发明授权

US09077361B1 Phase estimator 有权
标题翻译：相位估计器
公开(公告)号：US09077361B1
公开(公告)日：2015-07-07
申请号：US14551904
申请日：2014-11-24
申请人： NXP B.V.
发明人： Salvatore Drago
IPC分类号： H03M1/12 , H03M1/08 , H03M1/00 , H03M1/18 , H03M1/46 , H03M1/38
CPC分类号： H03M1/38 , H03M1/46 , H03M1/462 , H03M1/804 , H04L27/3818
摘要： A phase estimator comprising a first input terminal configured to receive a first analog input signal; a second input terminal configured to receive a second analog input signal, wherein the second analog input signal is 90° out of phase with the first analog input signal. The phase estimator is configured to provide a digital word representative of the phase of the first analog input signal and the second analog input signal. The phase estimator comprises a register configured to store N bits as a digital word a first reference signal generator, a second reference signal generator and a comparator.
摘要翻译：相位估计器，包括被配置为接收第一模拟输入信号的第一输入端; 第二输入端子，被配置为接收第二模拟输入信号，其中所述第二模拟输入信号与所述第一模拟输入信号相差90°。相位估计器被配置为提供表示第一模拟输入信号和第二模拟输入信号的相位的数字字。相位估计器包括被配置为将N位作为数字字存储的第一参考信号发生器，第二参考信号发生器和比较器的寄存器。

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