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1. 发明申请

US20090106588A1 Method and Apparatus for Parallel and Serial Data Transfer 有权
标题翻译：并行和串行数据传输的方法和装置
公开(公告)号：US20090106588A1
公开(公告)日：2009-04-23
申请号：US11874232
申请日：2007-10-18
申请人： Patrick J. Meaney , Ra'ed Mohammad Al-Omari , Michael Francis Fee , Pak-kin Mak , Scott Barnett Swaney
发明人： Patrick J. Meaney , Ra'ed Mohammad Al-Omari , Michael Francis Fee , Pak-kin Mak , Scott Barnett Swaney
IPC分类号： G06F11/14 , G06F9/46
CPC分类号： G06F11/10
摘要： A method and apparatus are disclosed for performing maintenance operations in a system using address, data, and controls which are transported through the system, allowing for parallel and serial operations to co-exist without the parallel operations being slowed down by the serial ones. It also provides for use of common shifters, engines, and protocols as well as efficient conversion of ECC to parity and parity to ECC as needed in the system. The invention also provides for error detection and isolation, both locally and in the reported status. The invention provides for large maintenance address and data spaces (typically 64 bits address and 64 bits data per address supported).
摘要翻译：公开了一种用于在通过系统传送的地址，数据和控制的系统中进行维护操作的方法和装置，允许并行和串行操作共存，而并行操作不被串行操作减慢。它还提供了常用的移位器，引擎和协议的使用，以及系统中根据需要将ECC高效地转换为奇偶校验和奇偶校验。本发明还提供了本地和报告状态的错误检测和隔离。本发明提供大的维护地址和数据空间（通常支持64位地址和64位数据）。

2. 发明授权

US08122297B2 Method and apparatus for parallel and serial data transfer 有权
标题翻译：并行和串行数据传输的方法和装置
公开(公告)号：US08122297B2
公开(公告)日：2012-02-21
申请号：US11874232
申请日：2007-10-18
申请人： Patrick J. Meaney , Ra'ed Mohammad Al-Omari , Michael Francis Fee , Pak-kin Mak , Scott Barnett Swaney
发明人： Patrick J. Meaney , Ra'ed Mohammad Al-Omari , Michael Francis Fee , Pak-kin Mak , Scott Barnett Swaney
IPC分类号： G06F11/00
CPC分类号： G06F11/10
摘要： A method and apparatus are disclosed for performing maintenance operations in a system using address, data, and controls which are transported through the system, allowing for parallel and serial operations to co-exist without the parallel operations being slowed down by the serial ones. It also provides for use of common shifters, engines, and protocols as well as efficient conversion of ECC to parity and parity to ECC as needed in the system. The invention also provides for error detection and isolation, both locally and in the reported status. The invention provides for large maintenance address and data spaces (typically 64 bits address and 64 bits data per address supported).
摘要翻译：公开了一种用于在通过系统传送的地址，数据和控制的系统中进行维护操作的方法和装置，允许并行和串行操作共存，而并行操作不被串行操作减慢。它还提供了常用的移位器，引擎和协议的使用，以及系统中根据需要将ECC高效地转换为奇偶校验和奇偶校验。本发明还提供了本地和报告状态的错误检测和隔离。本发明提供大的维护地址和数据空间（通常支持64位地址和64位数据）。

3. 发明授权

US07870406B2 Method and apparatus for frequency independent processor utilization recording register in a simultaneously multi-threaded processor 有权
标题翻译：用于频率独立处理器利用记录寄存器的同时多线程处理器的方法和装置
公开(公告)号：US07870406B2
公开(公告)日：2011-01-11
申请号：US11050325
申请日：2005-02-03
申请人： Richard Louis Arndt , Balaram Sinharoy , Scott Barnett Swaney , Kenneth Lundy Ward
发明人： Richard Louis Arndt , Balaram Sinharoy , Scott Barnett Swaney , Kenneth Lundy Ward
IPC分类号： G06F1/00
CPC分类号： G06F11/3442 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F11/3471 , G06F2201/88 , G06F2201/885 , Y02D10/126
摘要： Mechanism for accurately measuring useful capacity of a processor allocated to each thread in a simultaneously multi-threading data processing system. Instructions dispatched from multiple threads are executed by the processor on a same clock cycle. A determination is made whether Time Base (TB) register bit (60) is changing. A dispatch charge value is determined for each thread, and added to the Processor Utilization Resource Register for each thread when TB bit (60) changes.
摘要翻译：用于准确测量在同时多线程数据处理系统中分配给每个线程的处理器的有用容量的机制。从多个线程调度的指令由处理器以相同的时钟周期执行。确定时基（TB）寄存器位（60）是否改变。为每个线程确定调度费用值，并在TB位（60）更改时将其添加到每个线程的处理器利用资源寄存器中。

4. 发明申请

US20090113212A1 Multiprocessor electronic circuit including a plurality of processors and electronic data processing system 有权
标题翻译：多处理器电子电路包括多个处理器和电子数据处理系统
公开(公告)号：US20090113212A1
公开(公告)日：2009-04-30
申请号：US12248549
申请日：2008-10-09
申请人： Thomas Koehler , Thomas Fuchs , Ulrich Mayer , Chung-Lung Kevin Shum , Scott Barnett Swaney
发明人： Thomas Koehler , Thomas Fuchs , Ulrich Mayer , Chung-Lung Kevin Shum , Scott Barnett Swaney
IPC分类号： G06F21/00
CPC分类号： G06F21/72
摘要： A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.
摘要翻译：公开了一种包括这种电路的多处理器电子电路和电子数据处理系统，用于降低具有加密功能的多处理器系统的功耗和芯片面积消耗。在一个实施例中，多处理器电子电路包括多个处理器，包括多个输入/输出缓冲器对和两个加密引擎，密码引擎和哈希引擎以及相关控制逻辑的单个密码处理单元。

5. 发明申请

US20090063898A1 Processor Instruction Retry Recovery 失效
标题翻译：处理器指令重试恢复
公开(公告)号：US20090063898A1
公开(公告)日：2009-03-05
申请号：US12270300
申请日：2008-11-13
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/20
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

6. 发明授权

US07467325B2 Processor instruction retry recovery 有权
标题翻译：处理器指令重试恢复
公开(公告)号：US07467325B2
公开(公告)日：2008-12-16
申请号：US11055258
申请日：2005-02-10
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/00
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

7. 发明授权

US07418541B2 Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor 失效
标题翻译：用于间接访问内存映射资源的支持接口以减少带外支持处理器的系统连接的方法
公开(公告)号：US07418541B2
公开(公告)日：2008-08-26
申请号：US11055404
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
IPC分类号： G06F12/00 , G05B13/02 , G06F15/00 , G06F15/76
CPC分类号： G06F15/7842
摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.
摘要翻译：提供了一种用于存储器映射资源的支持接口的方法和装置。支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。内存映射支持接口更新内存，内存映射寄存器或内存映射资源。该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。系统还报告遇到的任何错误。

8. 发明授权

US08090823B2 Providing low-level hardware access to in-band and out-of-band firmware 失效
标题翻译：提供对带内和带外固件的低级硬件访问
公开(公告)号：US08090823B2
公开(公告)日：2012-01-03
申请号：US12259942
申请日：2008-10-28
申请人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
IPC分类号： G06F15/173 , G06F15/167
CPC分类号： G06F15/161
摘要： Illustrative embodiments disclose a data processing system providing low-level hardware access to in-band and out-of-band firmware. The data processing system includes a plurality of chips that includes at least one processor chip and a plurality of support chips. At least one processor chip includes a field replaceable unit support interface master that uses a field replaceable unit support interface serial transmission protocol to communicate with the plurality of support chips. Each one of the plurality of support chips includes a field replaceable unit support interface slave in, with ones of the plurality of chips that include a processor also include the field replaceable unit support interface master, and ones of the plurality of chips that do not include the processor include only the field replaceable unit support interface slave. Only the field replaceable unit support interface master possesses conversion logic.
摘要翻译：说明性实施例公开了提供对带内和带外固件的低级硬件访问的数据处理系统。数据处理系统包括多个芯片，其包括至少一个处理器芯片和多个支持芯片。至少一个处理器芯片包括使用现场可更换单元支持接口串行传输协议与多个支持芯片进行通信的现场可更换单元支持接口主机。多个支持芯片中的每一个包括现场可更换单元支持接口从机，其中包括处理器的多个芯片中的一个包括现场可更换单元支持接口主机，以及不包括的多个芯片中的一个处理器仅包括现场可更换单元支持接口从站。只有现场可更换单元支持接口主机具有转换逻辑。

9. 发明授权

US07840860B2 Double DRAM bit steering for multiple error corrections 失效
标题翻译：双重DRAM位转向可进行多次错误更正
公开(公告)号：US07840860B2
公开(公告)日：2010-11-23
申请号：US12188033
申请日：2008-08-07
申请人： Luiz Carlos Alves , Mark Andrew Brittain , Timothy Jay Dell , Sanjeev Ghai , Warren Edward Maule , Scott Barnett Swaney
发明人： Luiz Carlos Alves , Mark Andrew Brittain , Timothy Jay Dell , Sanjeev Ghai , Warren Edward Maule , Scott Barnett Swaney
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G06F11/1044 , G11C5/04 , G11C29/4401 , G11C29/76 , G11C29/846 , G11C2029/0409
摘要： A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.
摘要翻译：提出了一种用于校正双列直插式存储器模块（DIMM）中的主动态随机存取存储器（DRAM）中的数据错误的方法和系统。每个DRAM具有左半部分（用于存储位0：3）和右半部分（用于存储位4：7）。确定数据错误是在主DRAM的左半还是右半部。发生错误的主要DRAM的一半从服务中删除。原始存储在主DRAM缺陷半部分的数据的所有后续读取和写入都被制成DIMM中的备用DRAM的一半，而DRAM的无缺陷半部分继续用于随后存储数据。

10. 发明授权

US07761726B2 Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer 失效
标题翻译：可扩展多处理器计算机中的容错时间同步机制的方法和装置
公开(公告)号：US07761726B2
公开(公告)日：2010-07-20
申请号：US12116652
申请日：2008-05-07
申请人： Scott Barnett Swaney , Kenneth Lundy Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
发明人： Scott Barnett Swaney , Kenneth Lundy Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
IPC分类号： G06F1/12
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译：冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。独立的步进同步信号被传送到几个同级芯片。本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。所有剩余的芯片都是从芯片。拓扑的所有段都是冗余的。多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

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