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1. 发明授权

US08793512B2 Method and apparatus for thermal control of processing nodes 有权
标题翻译：处理节点热控制的方法和装置
公开(公告)号：US08793512B2
公开(公告)日：2014-07-29
申请号：US12915361
申请日：2010-10-29
申请人： Alexander Branover , Samuel D. Naffziger
发明人： Alexander Branover , Samuel D. Naffziger
IPC分类号： G01K1/00 , G01K7/00
CPC分类号： G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D50/20
摘要： An apparatus and method for per-node thermal control of processing nodes is disclosed. The apparatus includes a plurality of processing nodes, and further includes a power management unit configured to set a first frequency limit for at least one of the plurality of processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold, wherein the first detected temperature is associated with the one of the plurality of processing nodes. The power management unit is further configured to set a second frequency limit for each of the plurality of processing nodes responsive to receiving an indication of a second temperature greater than a second temperature threshold.
摘要翻译：公开了一种用于处理节点的每节点热控制的装置和方法。该装置包括多个处理节点，并且还包括功率管理单元，其被配置为响应于接收到大于第一温度阈值的第一检测温度的指示来设置多个处理节点中的至少一个的第一频率限制，其中所述第一检测温度与所述多个处理节点中的一个相关联。功率管理单元还被配置为响应于接收到大于第二温度阈值的第二温度的指示，为多个处理节点中的每一个设置第二频率限制。

2. 发明申请

US20120110352A1 METHOD AND APPARATUS FOR THERMAL CONTROL OF PROCESSING NODES 有权
标题翻译：加工过程热控制的方法与装置
公开(公告)号：US20120110352A1
公开(公告)日：2012-05-03
申请号：US12915361
申请日：2010-10-29
申请人： Alexander Branover , Samuel D. Naffziger
发明人： Alexander Branover , Samuel D. Naffziger
IPC分类号： G06F1/26 , H01L37/00
CPC分类号： G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D50/20
摘要： An apparatus and method for per-node thermal control of processing nodes is disclosed. The apparatus includes a plurality of processing nodes, and further includes a power management unit configured to set a first frequency limit for at least one of the plurality of processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold, wherein the first detected temperature is associated with the one of the plurality of processing nodes. The power management unit is further configured to set a second frequency limit for each of the plurality of processing nodes responsive to receiving an indication of a second temperature greater than a second temperature threshold.
摘要翻译：公开了一种用于处理节点的每节点热控制的装置和方法。该装置包括多个处理节点，并且还包括功率管理单元，其被配置为响应于接收到大于第一温度阈值的第一检测温度的指示来设置多个处理节点中的至少一个的第一频率限制，其中所述第一检测温度与所述多个处理节点中的一个相关联。功率管理单元还被配置为响应于接收到大于第二温度阈值的第二温度的指示，为多个处理节点中的每一个设置第二频率限制。

3. 发明申请

US20120054515A1 MECHANISM FOR VOLTAGE REGULATOR LOAD LINE COMPENSATION USING MULTIPLE VOLTAGE SETTINGS PER OPERATING STATE 有权
标题翻译：运行状态下使用多个电压设置的电压调节器负载线补偿机制
公开(公告)号：US20120054515A1
公开(公告)日：2012-03-01
申请号：US12872414
申请日：2010-08-31
申请人： Samuel D. Naffziger , Alexander Branover
发明人： Samuel D. Naffziger , Alexander Branover
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A system includes one or more processor cores, and a voltage regulator that provides an operating voltage to the one or more processor cores in response to receiving a voltage identifier signal that is indicative of the operating voltage. The system also includes a power management unit that may provide a first voltage identifier signal corresponding to a first operating voltage in response to determining that the processor cores are operating in a first operating state in which the one or more processor cores may draw up to a maximum load current. The power management unit may also provide a second voltage identifier signal corresponding to a second operating voltage, which is less than the first operating voltage, in response to determining that the processor cores are operating in a second operating state in which the processor cores are incapable of an increase in load current above a predetermined amount.
摘要翻译：系统包括一个或多个处理器核心和电压调节器，其响应于接收到指示工作电压的电压标识符信号而向一个或多个处理器核心提供工作电压。该系统还包括功率管理单元，其可以响应于确定处理器核在第一操作状态下操作而提供与第一工作电压相对应的第一电压标识符信号，其中一个或多个处理器核可以绘制到最大负载电流。电源管理单元还可以响应于确定处理器核在其中处理器核不能够处于第二操作状态的操作而提供对应于小于第一工作电压的第二工作电压的第二电压标识符信号负载电流的增加高于预定量。

4. 发明授权

US08463973B2 Mechanism for voltage regulator load line compensation using multiple voltage settings per operating state 有权
标题翻译：使用多个电压设置每个工作状态的电压调节器负载线路补偿的机制
公开(公告)号：US08463973B2
公开(公告)日：2013-06-11
申请号：US12872414
申请日：2010-08-31
申请人： Samuel D. Naffziger , Alexander Branover
发明人： Samuel D. Naffziger , Alexander Branover
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A system includes one or more processor cores, and a voltage regulator that provides an operating voltage to the one or more processor cores in response to receiving a voltage identifier signal that is indicative of the operating voltage. The system also includes a power management unit that may provide a first voltage identifier signal corresponding to a first operating voltage in response to determining that the processor cores are operating in a first operating state in which the one or more processor cores may draw up to a maximum load current. The power management unit may also provide a second voltage identifier signal corresponding to a second operating voltage, which is less than the first operating voltage, in response to determining that the processor cores are operating in a second operating state in which the processor cores are incapable of an increase in load current above a predetermined amount.
摘要翻译：系统包括一个或多个处理器核心和电压调节器，其响应于接收到指示工作电压的电压标识符信号而向一个或多个处理器内核提供工作电压。该系统还包括功率管理单元，其可以响应于确定处理器核在第一操作状态下操作而提供与第一工作电压相对应的第一电压标识符信号，其中一个或多个处理器核可以绘制到最大负载电流。电源管理单元还可以响应于确定处理器核在其中处理器核不能够处于第二操作状态的操作而提供对应于小于第一工作电压的第二工作电压的第二电压标识符信号负载电流的增加高于预定量。

5. 发明授权

US08975936B2 Constraining clock skew in a resonant clocked system 有权
标题翻译：在谐振时钟系统中约束时钟偏移
公开(公告)号：US08975936B2
公开(公告)日：2015-03-10
申请号：US13601119
申请日：2012-08-31
申请人： Visvesh S. Sathe , Samuel D. Naffziger
发明人： Visvesh S. Sathe , Samuel D. Naffziger
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.
摘要翻译：集成电路包括谐振时钟网络的多个谐振时钟域。每个谐振时钟域具有至少一个时钟驱动器，其将一部分时钟信号提供给相关联的谐振时钟域。谐振时钟网络以谐振模式工作，其中电感器连接到谐振时钟域之间边界处的谐振时钟域对。每个电感器在电感器所连接的一对谐振时钟域中形成具有时钟负载电容的LC电路。

6. 发明授权

US08854100B2 Clock driver for frequency-scalable systems 有权
标题翻译：用于频率可伸缩系统的时钟驱动器
公开(公告)号：US08854100B2
公开(公告)日：2014-10-07
申请号：US13601188
申请日：2012-08-31
申请人： Visvesh S. Sathe , Samuel D. Naffziger , Srikanth Arekapudi
发明人： Visvesh S. Sathe , Samuel D. Naffziger , Srikanth Arekapudi
IPC分类号： G06F1/04 , H03K3/00 , H03K19/003
CPC分类号： H03K19/003 , G06F1/10
摘要： A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.
摘要翻译：用于谐振时钟网络的时钟驱动器包括接收并提供延迟的时钟信号的延迟电路。第一晶体管被耦合以接收第一脉冲控制信号并提供时钟驱动器的输出时钟节点。第一控制信号的有效边沿响应延迟的时钟信号的下降沿。第二晶体管被耦合以接收第二控制信号并提供时钟驱动器的输出时钟节点。第二控制信号的有效边沿响应延迟的时钟信号的上升沿。

7. 发明授权

US08495395B2 Mechanism for controlling power consumption in a processing node 有权
标题翻译：控制处理节点功耗的机制
公开(公告)号：US08495395B2
公开(公告)日：2013-07-23
申请号：US12881307
申请日：2010-09-14
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system includes a plurality of processor cores and a power management unit. The power management unit may be configured to independently control the performance of the processor cores by selecting a respective thermal power limit for each of the plurality of processor cores dependent upon an operating state of each of the processor cores and a relative physical proximity of each processor core to each other processor core. In response to the power management unit detecting that a given processor core is operating above the respective thermal power limit, the power management unit may reduce the performance of the given processor core, and thereby reduce the power consumed by that core.
摘要翻译：系统包括多个处理器核心和电源管理单元。功率管理单元可以被配置为通过根据每个处理器核心的操作状态和每个处理器的相对物理接近度来选择对于多个处理器核心中的每一个的相应的热功率限制来独立地控制处理器核心的性能核心到对方处理器核心。响应于电源管理单元检测到给定的处理器内核正在高于相应的热功率限制，功率管理单元可以降低给定的处理器核心的性能，从而减少该核心的功耗。

8. 发明申请

US20120159198A1 PROCESSOR POWER LIMIT MANAGEMENT 有权
标题翻译：处理器功率限制管理
公开(公告)号：US20120159198A1
公开(公告)日：2012-06-21
申请号：US12970172
申请日：2010-12-16
申请人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
发明人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a measured power dissipation within the processor. A power controller is configured to adjust a processor power parameter based on the power target and the measured power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the measured dissipation stays below the processor power target, software processor power target and the agent processor power target.
摘要翻译：提供了一种处理器功率限制器和方法。处理器包括被配置为存储处理器功率目标的第一可编程位置。功率监视器被配置为估计处理器内的测量功率耗散。功率控制器被配置为基于功率目标和测量的功率耗散来调整处理器功率参数。处理器可以包括用于操作系统的接口。可以将第二可编程位置配置为存储由操作系统可访问的软件处理器功率目标。处理器还可以包括用于外部代理的边带接口。可以将第三可编程位置配置为存储由外部代理可访问的代理处理器功率目标。功率控制器可以被配置为调整处理器核心电压和/或频率，使得所测量的功率保持在处理器功率目标，软件处理器功率目标和代理处理器功率目标之下。

9. 发明授权

US08195962B2 Method and apparatus for regulating power consumption 有权
标题翻译：调节功耗的方法和装置
公开(公告)号：US08195962B2
公开(公告)日：2012-06-05
申请号：US12268531
申请日：2008-11-11
申请人： Samuel D. Naffziger , Sebastien J. Nussbaum
发明人： Samuel D. Naffziger , Sebastien J. Nussbaum
IPC分类号： G06F1/32 , G06F1/26 , G06F11/30
CPC分类号： G06F1/206 , G06F1/3203 , G06F9/50 , Y02D10/16 , Y02D10/22
摘要： A method for controlling power consumption while maximizing processor performance. The method includes, for a time interval of operation in a first operational state, determining an amount of power consumed during by one or more cores of a processor, calculating, a power error based on the amount of power consumed in the time interval, obtaining a power error term for the interval by adding the power error to a power error term from a previous time interval, and comparing the power error term to at least a first error threshold. If the power error term is outside a range defined at least in part by the first error threshold, the method exits the first operational state and enters a second operational state. If the power error term is within the range defined at least in part by the first error threshold, operation continues in the first operational state.
摘要翻译：一种在最大化处理器性能的同时控制功耗的方法。该方法包括：在第一操作状态下的操作的时间间隔中，确定处理器的一个或多个核心期间消耗的功率量，基于在该时间间隔中消耗的功率量来计算功率误差，获得通过将功率误差添加到来自前一时间间隔的功率误差项，以及将功率误差项与至少第一误差阈值进行比较来计算间隔的功率误差项。如果功率误差项在至少部分由第一误差阈值限定的范围之外，则该方法退出第一操作状态并进入第二操作状态。如果功率误差项在至少部分地由第一误差阈值限定的范围内，则操作在第一操作状态下继续。

10. 发明授权

US08193799B2 Interposer including voltage regulator and method therefor 有权
标题翻译：内插器包括电压调节器及其方法
公开(公告)号：US08193799B2
公开(公告)日：2012-06-05
申请号：US12236003
申请日：2008-09-23
申请人： Stephen V. Kosonocky , Samuel D. Naffziger , Visvesh S. Sathe
发明人： Stephen V. Kosonocky , Samuel D. Naffziger , Visvesh S. Sathe
IPC分类号： B23K11/24
CPC分类号： H01L25/16 , H01L25/0657 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H05K1/0262 , H05K2201/10378 , Y10T307/406 , H01L2224/0401
摘要： A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device.
摘要翻译：公开了一种包括被称为集成电路插入器的电子设备的装置。集成电路包括电压调节器模块。插入器附接到诸如另一集成电路的电子设备，并且便于对电子设备的电力的控制和分配。集成电路插入器还可以在附接的电子设备和另一电子设备之间进行信令。集成电路插入器上的电压调节器模块可以被配置为向附接的电子设备提供电压参考信号。根据电子设备的工作要求，可以使能或禁止由集成电路插入器产生电压参考信号，并且可以调节电压参考信号的值。

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