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1. 发明申请

US20120054515A1 MECHANISM FOR VOLTAGE REGULATOR LOAD LINE COMPENSATION USING MULTIPLE VOLTAGE SETTINGS PER OPERATING STATE 有权
标题翻译：运行状态下使用多个电压设置的电压调节器负载线补偿机制
公开(公告)号：US20120054515A1
公开(公告)日：2012-03-01
申请号：US12872414
申请日：2010-08-31
申请人： Samuel D. Naffziger , Alexander Branover
发明人： Samuel D. Naffziger , Alexander Branover
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A system includes one or more processor cores, and a voltage regulator that provides an operating voltage to the one or more processor cores in response to receiving a voltage identifier signal that is indicative of the operating voltage. The system also includes a power management unit that may provide a first voltage identifier signal corresponding to a first operating voltage in response to determining that the processor cores are operating in a first operating state in which the one or more processor cores may draw up to a maximum load current. The power management unit may also provide a second voltage identifier signal corresponding to a second operating voltage, which is less than the first operating voltage, in response to determining that the processor cores are operating in a second operating state in which the processor cores are incapable of an increase in load current above a predetermined amount.
摘要翻译：系统包括一个或多个处理器核心和电压调节器，其响应于接收到指示工作电压的电压标识符信号而向一个或多个处理器核心提供工作电压。该系统还包括功率管理单元，其可以响应于确定处理器核在第一操作状态下操作而提供与第一工作电压相对应的第一电压标识符信号，其中一个或多个处理器核可以绘制到最大负载电流。电源管理单元还可以响应于确定处理器核在其中处理器核不能够处于第二操作状态的操作而提供对应于小于第一工作电压的第二工作电压的第二电压标识符信号负载电流的增加高于预定量。

2. 发明授权

US08793512B2 Method and apparatus for thermal control of processing nodes 有权
标题翻译：处理节点热控制的方法和装置
公开(公告)号：US08793512B2
公开(公告)日：2014-07-29
申请号：US12915361
申请日：2010-10-29
申请人： Alexander Branover , Samuel D. Naffziger
发明人： Alexander Branover , Samuel D. Naffziger
IPC分类号： G01K1/00 , G01K7/00
CPC分类号： G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D50/20
摘要： An apparatus and method for per-node thermal control of processing nodes is disclosed. The apparatus includes a plurality of processing nodes, and further includes a power management unit configured to set a first frequency limit for at least one of the plurality of processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold, wherein the first detected temperature is associated with the one of the plurality of processing nodes. The power management unit is further configured to set a second frequency limit for each of the plurality of processing nodes responsive to receiving an indication of a second temperature greater than a second temperature threshold.
摘要翻译：公开了一种用于处理节点的每节点热控制的装置和方法。该装置包括多个处理节点，并且还包括功率管理单元，其被配置为响应于接收到大于第一温度阈值的第一检测温度的指示来设置多个处理节点中的至少一个的第一频率限制，其中所述第一检测温度与所述多个处理节点中的一个相关联。功率管理单元还被配置为响应于接收到大于第二温度阈值的第二温度的指示，为多个处理节点中的每一个设置第二频率限制。

3. 发明授权

US08463973B2 Mechanism for voltage regulator load line compensation using multiple voltage settings per operating state 有权
标题翻译：使用多个电压设置每个工作状态的电压调节器负载线路补偿的机制
公开(公告)号：US08463973B2
公开(公告)日：2013-06-11
申请号：US12872414
申请日：2010-08-31
申请人： Samuel D. Naffziger , Alexander Branover
发明人： Samuel D. Naffziger , Alexander Branover
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A system includes one or more processor cores, and a voltage regulator that provides an operating voltage to the one or more processor cores in response to receiving a voltage identifier signal that is indicative of the operating voltage. The system also includes a power management unit that may provide a first voltage identifier signal corresponding to a first operating voltage in response to determining that the processor cores are operating in a first operating state in which the one or more processor cores may draw up to a maximum load current. The power management unit may also provide a second voltage identifier signal corresponding to a second operating voltage, which is less than the first operating voltage, in response to determining that the processor cores are operating in a second operating state in which the processor cores are incapable of an increase in load current above a predetermined amount.
摘要翻译：系统包括一个或多个处理器核心和电压调节器，其响应于接收到指示工作电压的电压标识符信号而向一个或多个处理器内核提供工作电压。该系统还包括功率管理单元，其可以响应于确定处理器核在第一操作状态下操作而提供与第一工作电压相对应的第一电压标识符信号，其中一个或多个处理器核可以绘制到最大负载电流。电源管理单元还可以响应于确定处理器核在其中处理器核不能够处于第二操作状态的操作而提供对应于小于第一工作电压的第二工作电压的第二电压标识符信号负载电流的增加高于预定量。

4. 发明申请

US20120110352A1 METHOD AND APPARATUS FOR THERMAL CONTROL OF PROCESSING NODES 有权
标题翻译：加工过程热控制的方法与装置
公开(公告)号：US20120110352A1
公开(公告)日：2012-05-03
申请号：US12915361
申请日：2010-10-29
申请人： Alexander Branover , Samuel D. Naffziger
发明人： Alexander Branover , Samuel D. Naffziger
IPC分类号： G06F1/26 , H01L37/00
CPC分类号： G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D50/20
摘要： An apparatus and method for per-node thermal control of processing nodes is disclosed. The apparatus includes a plurality of processing nodes, and further includes a power management unit configured to set a first frequency limit for at least one of the plurality of processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold, wherein the first detected temperature is associated with the one of the plurality of processing nodes. The power management unit is further configured to set a second frequency limit for each of the plurality of processing nodes responsive to receiving an indication of a second temperature greater than a second temperature threshold.
摘要翻译：公开了一种用于处理节点的每节点热控制的装置和方法。该装置包括多个处理节点，并且还包括功率管理单元，其被配置为响应于接收到大于第一温度阈值的第一检测温度的指示来设置多个处理节点中的至少一个的第一频率限制，其中所述第一检测温度与所述多个处理节点中的一个相关联。功率管理单元还被配置为响应于接收到大于第二温度阈值的第二温度的指示，为多个处理节点中的每一个设置第二频率限制。

5. 发明授权

US08566628B2 North-bridge to south-bridge protocol for placing processor in low power state 有权
标题翻译：用于将处理器置于低功率状态的北桥南桥协议
公开(公告)号：US08566628B2
公开(公告)日：2013-10-22
申请号：US12436439
申请日：2009-05-06
申请人： Alexander Branover , Maurice B. Steinman , Ming L. So , Xiao Gang Zheng
发明人： Alexander Branover , Maurice B. Steinman , Ming L. So , Xiao Gang Zheng
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.
摘要翻译：处理器集成电路具有一个或多个处理器核心和北桥中的功率管理控制器，其为一个或多个处理器核心生成第一功率状态推荐。北桥还从南桥集成电路获得了第二个功率状态建议。北桥基于第一和第二功率状态建议确定一个或多个处理器核的最终功率状态。

6. 发明申请

US20120102344A1 FUNCTION BASED DYNAMIC POWER CONTROL 有权
标题翻译：基于功能的动态功率控制
公开(公告)号：US20120102344A1
公开(公告)日：2012-04-26
申请号：US12909006
申请日：2010-10-21
申请人： Andrej Kocev , Alexander Branover
发明人： Andrej Kocev , Alexander Branover
IPC分类号： G06F1/00
CPC分类号： G06F1/3237 , G06F1/3275 , G06F1/3287 , Y02D10/128 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same.
摘要翻译：公开了一种用于基于动态功能的功率控制的系统和方法。在一个实施例中，系统包括具有存储器控制器和耦合到存储器控制器的通信集线器的桥接单元。该系统还包括电力管理单元，其中电力管理单元被配置为响应于确定多个处理器核心中的每一个处于空闲状态并且I / O接口单元已经空闲而对通信集线器进行时钟门超过第一阈值的时间量。电源管理单元还被配置为响应于时钟门控通信集线器来对存储器控制器进行时钟门控，并且确定耦合到存储器控制器的存储器处于第一低功率状态。功率管理单元还可以在其门控门控之后执行功能单元的功率门控。

7. 发明申请

US20120054519A1 DYNAMIC PERFORMANCE CONTROL OF PROCESSING NODES 有权
标题翻译：加工过程动态性能控制
公开(公告)号：US20120054519A1
公开(公告)日：2012-03-01
申请号：US12868996
申请日：2010-08-26
申请人： Alexander Branover , Maurice Steinman , William L. Bircher
发明人： Alexander Branover , Maurice Steinman , William L. Bircher
IPC分类号： G06F1/32
CPC分类号： G06F1/3215 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.
摘要翻译：公开了一种用于处理节点的性能控制的装置和方法。在一个实施例中，系统包括处理节点和功率管理单元，其被配置为针对多个时间间隔中的每一个监视处理节点的活动级别，使处理节点在连续的连续操作期间在高操作点时间间隔，如果给定间隔中的活动水平大于高活动阈值，则如果活动水平低于低活动阈值，则在低操作点操作至少一个连续时间间隔，或使得操作系统软件能够使处理节点在多个操作点的一个或多个预定义的中间操作点之一操作，如果活动水平小于高活动阈值并且大于低活动阈值。

8. 发明授权

US09021209B2 Cache flush based on idle prediction and probe activity level 有权
标题翻译：基于空闲预测和探测活动级别的缓存刷新
公开(公告)号：US09021209B2
公开(公告)日：2015-04-28
申请号：US12702085
申请日：2010-02-08
申请人： Alexander Branover , Maurice B. Steinman
发明人： Alexander Branover , Maurice B. Steinman
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F1/3203 , G06F12/0831 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests.
摘要翻译：处理节点跟踪与其高速缓存相关联的探测活动级别。处理节点和/或处理系统进一步预测空闲持续时间。如果探测器活动级别增加到高于阈值探测器活动级别，并且空闲持续时间预测高于阈值空闲持续时间阈值，则处理节点刷新其高速缓存以防止对高速缓存的探测。如果探测器活动级别高于阈值探测器活动级别，但是预测的空闲持续时间太短，则处理节点的性能状态增加到高于其当前性能状态，以提供响应探测请求的增强的性能能力。

9. 发明授权

US08656198B2 Method and apparatus for memory power management 有权
标题翻译：用于存储器电源管理的方法和装置
公开(公告)号：US08656198B2
公开(公告)日：2014-02-18
申请号：US12767460
申请日：2010-04-26
申请人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
发明人： Alexander Branover , Maurice B. Steinman , Anthony Asaro , James B. Fry
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C5/148 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.
摘要翻译：公开了一种用于电力管理的方法。该方法可以包括监视由一个或多个处理器核访问存储器子系统的存储器的请求; 以及监视对由输入/输出（I / O）单元传送的存储器的访问请求。该方法还可以包括确定是否已经过去了至少第一时间量，因为处理器核心已经确定了存储器访问请求并且确定自I / O单元是否已经传送了至少第二时间量内存访问请求。如果第一和第二时间量已经过去，则可以断言第一信号。存储器子系统可以响应于第一信号的断言而从全功率状态工作转变到第一低功率状态。

10. 发明授权

US08291249B2 Method and apparatus for transitioning devices between power states based on activity request frequency 有权
标题翻译：基于活动请求频率在设备状态之间转换设备的方法和装置
公开(公告)号：US08291249B2
公开(公告)日：2012-10-16
申请号：US12566930
申请日：2009-09-25
申请人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
发明人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , Y02D10/126
摘要： A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.
摘要翻译：用于转换设备中的电源状态的方法包括：将第一降低功率状态指定为目标功率状态。基于对与设备相关联的活动请求的计数来确定目标电力状态的第一预期驻留。响应于满足第一预定阈值的预期驻留，该设备被转换到目标功率状态。

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