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1. 发明授权

US08705287B2 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08705287B2
公开(公告)日：2014-04-22
申请号：US13282029
申请日：2011-10-26
申请人： Seiichi Aritome , Soo Jin Wi , Angelo Visconti , Mattia Robustelli
发明人： Seiichi Aritome , Soo Jin Wi , Angelo Visconti , Mattia Robustelli
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/3459 , G11C16/06 , G11C16/3454 , G11C16/3468
摘要： A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.
摘要翻译：一种操作半导体存储器件的方法包括执行第一程序操作以提高存储单元的阈值电压，执行用于检测快速程序存储单元的程序验证操作，每个程序存储单元的阈值电压升高高于第一次验证电压通过使用目标验证电压和顺序地低于目标验证电压的第一子验证电压和第二子验证电压，从第二子验证电压或更低的次级验证电压进行第二子验证电压，并且在低于目标验证电压的存储单元的每个阈值电压的增量大于每个快速程序存储单元的阈值电压的增量。

2. 发明授权

US08493792B2 Programming method of non-volatile memory device 有权
标题翻译：非易失性存储器件的编程方法
公开(公告)号：US08493792B2
公开(公告)日：2013-07-23
申请号：US13309760
申请日：2011-12-02
申请人： Seiichi Aritome , Soo Jin Wi
发明人： Seiichi Aritome , Soo Jin Wi
IPC分类号： G11C16/06 , G11C11/56
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/3418 , G11C16/349
摘要： A programming method includes setting the voltages of bit lines, performing a program operation, performing a program verify operation by supplying a program verify voltage and determining whether all of the memory cells of the selected page have been programmed with a target threshold voltage or higher, counting the number of passed memory cells corresponding to a number of pass bits, if, a result of the program verify operation, the program operation failed to program all of the memory cells of the selected page to the target threshold voltage or higher, and making a determination that determines whether the number of pass bits is greater than the first number of pass permission bits, and raising a voltage of a bit line coupled to a failed memory cell, if, as a result of the determination, the number of pass bits is greater than the first number of pass permission bits.
摘要翻译：一种编程方法，包括设置位线的电压，执行编程操作，通过提供编程验证电压并确定所选择的页面的所有存储单元是否已经被编程为目标阈值电压或更高，执行编程验证操作，对与多个通过位相对应的经过的存储单元的数量进行计数，如果程序验证操作的结果，程序操作不能将所选页的所有存储单元编程为目标阈值电压或更高，并且使确定通过位的数量是否大于第一数量的通过许可位，并且提高耦合到故障存储器单元的位线的电压，如果作为确定的结果，通过位的数量大于第一个通过许可位数。

3. 发明申请

US20130033937A1 METHODS FOR PROGRAM VERIFYING A MEMORY CELL AND MEMORY DEVICES CONFIGURED TO PERFORM THE SAME 有权
标题翻译：用于程序验证存储器单元的方法和配置为执行其的存储器件
公开(公告)号：US20130033937A1
公开(公告)日：2013-02-07
申请号：US13204029
申请日：2011-08-05
申请人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
发明人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： A method for program verify is disclosed, such as one in which a threshold voltage of a memory cell that has been biased with a programming voltage can be determined and its relationship with multiple program verify voltage ranges can be determined. The program verify voltage range in which the threshold voltage is located determines the subsequent bit line voltage. The subsequent bit line voltage may be less than a previous bit line voltage used to program the memory cell.
摘要翻译：公开了一种用于程序验证的方法，例如可以确定已经用编程电压偏置的存储器单元的阈值电压并且可以确定其与多个程序验证电压范围的关系的方法。程序验证阈值电压所在的电压范围决定后续的位线电压。随后的位线电压可以小于用于对存储器单元进行编程的先前位线电压。

4. 发明授权

US08670273B2 Methods for program verifying a memory cell and memory devices configured to perform the same 有权
标题翻译：用于程序验证被配置为执行相同的存储器单元和存储器件的方法
公开(公告)号：US08670273B2
公开(公告)日：2014-03-11
申请号：US13204029
申请日：2011-08-05
申请人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
发明人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： A method for program verify is disclosed, such as one in which a threshold voltage of a memory cell that has been biased with a programming voltage can be determined and its relationship with multiple program verify voltage ranges can be determined. The program verify voltage range in which the threshold voltage is located determines the subsequent bit line voltage. The subsequent bit line voltage may be less than a previous bit line voltage used to program the memory cell.
摘要翻译：公开了一种用于程序验证的方法，例如可以确定已经用编程电压偏置的存储器单元的阈值电压并且可以确定其与多个程序验证电压范围的关系的方法。程序验证阈值电压所在的电压范围决定后续的位线电压。随后的位线电压可以小于用于对存储器单元进行编程的先前位线电压。

5. 发明授权

US08619475B2 Methods to operate a memory cell 有权
标题翻译：操作存储单元的方法
公开(公告)号：US08619475B2
公开(公告)日：2013-12-31
申请号：US13204014
申请日：2011-08-05
申请人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
发明人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C11/5628 , G11C16/3459
摘要： Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been biased with a programming voltage is determined and its relationship with the two program verify levels is determined. If the threshold voltage is less than the low program verify level, the data line can be biased at a ground voltage (e.g., 0V) for a subsequent programming pulse. If the threshold voltage is greater than the program verify level, the data line can be biased at an inhibit voltage for a subsequent programming pulse. If the threshold voltage is between the two program verify levels, the data line voltage can be increased for each subsequent programming pulse in which the threshold voltage is between the two program verify levels.
摘要翻译：公开了用于操作存储器单元的存储器件和方法，诸如使用两个程序验证电平（例如，低程序验证电平和程序验证电平）来确定如何增加数据线电压的方法。确定已经用编程电压偏置的存储单元的阈值电压，并确定其与两个程序验证电平的关系。如果阈值电压小于低编程验证电平，则可以将数据线偏置在接地电压（例如0V）以用于随后的编程脉冲。如果阈值电压大于程序验证电平，则数据线可以被偏置在用于后续编程脉冲的禁止电压。如果阈值电压在两个程序验证电平之间，则对于其中阈值电压在两个程序验证电平之间的每个后续编程脉冲，可以增加数据线电压。

6. 发明授权

US09058878B2 Read methods of semiconductor memory device 有权
标题翻译：读取半导体存储器件的方法
公开(公告)号：US09058878B2
公开(公告)日：2015-06-16
申请号：US13341303
申请日：2011-12-30
申请人： Seiichi Aritome , Soon Ok Seo
发明人： Seiichi Aritome , Soon Ok Seo
IPC分类号： G11C16/04 , G11C11/56 , G11C16/26
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26
摘要： A read method of a semiconductor memory device includes performing a read operation on target cells by using a first read voltage, terminating the read operation on the target cells if, as a result of the read operation on the target cells, error correction is feasible, performing a read operation on first cells next to the target cells along a first direction if, as a result of the read operation on the target cells, error correction is unfeasible, performing the read operation again on the target cells by selecting one of a plurality of read voltages in response to a result of the read operation on the first cells and by using the selected read voltage for reading data of the target cells, and terminating the read operation on the target cells if error correction is feasible.
摘要翻译：半导体存储器件的读取方法包括通过使用第一读取电压对目标单元执行读取操作，如果作为对目标单元的读取操作的结果，错误校正是可行的，则终止对目标单元的读取操作，如果作为对目标单元的读取操作的结果，误差校正是不可行的，则对目标单元的旁边的第一单元执行读取操作，通过选择多个目标单元之一对目标单元执行再次操作的读取电压，并且通过使用所选择的读取电压来读取目标单元的数据，并且如果纠错是可行的，则终止对目标单元的读取操作。

7. 发明授权

US09019767B2 Nonvolatile memory device and operating method thereof 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US09019767B2
公开(公告)日：2015-04-28
申请号：US13398397
申请日：2012-02-16
申请人： Seiichi Aritome , Hyun-Seung Yoo , Sung-Jin Whang
发明人： Seiichi Aritome , Hyun-Seung Yoo , Sung-Jin Whang
IPC分类号： G11C16/04 , H01L27/115 , G11C16/14
CPC分类号： G11C16/14 , G11C16/0408 , H01L27/11556 , H01L27/11582
摘要： A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.
摘要翻译：非易失性存储器件包括从衬底垂直延伸的沟道，沿着沟道堆叠的多个存储单元; 连接到所述沟道的第一端部的源极区域和与所述沟道的第二端部连接的位线，其中与所述源极区域相邻的所述沟道的所述第一端部形成为未掺杂的半导体层或半导体层掺杂有P型杂质。

8. 发明授权

US08441058B2 Memory devices having reduced interference between floating gates and methods of fabricating such devices 有权
公开(公告)号：US08441058B2
公开(公告)日：2013-05-14
申请号：US13180361
申请日：2011-07-11
申请人： Seiichi Aritome
发明人： Seiichi Aritome
IPC分类号： H01L29/788
CPC分类号： H01L21/762 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.

9. 发明申请

US20130107602A1 3-D NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译： 3-D非易失性存储器件及其制造方法
公开(公告)号：US20130107602A1
公开(公告)日：2013-05-02
申请号：US13601531
申请日：2012-08-31
申请人： Sang Hyun OH , Seiichi Aritome , Sang Bum LEE
发明人： Sang Hyun OH , Seiichi Aritome , Sang Bum LEE
IPC分类号： H01L27/088 , H01L21/336 , G11C5/02
CPC分类号： H01L27/11556 , G11C16/0408 , G11C16/14 , H01L21/8221 , H01L27/11524 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： A three-dimensional (3-D) nonvolatile memory device includes a channel layer protruded from a substrate, a plurality of memory cells stacked along the channel layer, a source line coupled to the end of one side of the channel layer, a bit line coupled to the end of the other side of the channel layer, a first junction interposed between the end of one side of the channel layer and the source line and configured to have a P type impurity doped therein, and a second junction interposed between the end of the other side of the channel layer and the bit line and configured to have an N type impurity doped therein.
摘要翻译：三维（3-D）非易失性存储器件包括从衬底突出的沟道层，沿着沟道层堆叠的多个存储单元，耦合到沟道层一侧的端部的源极线，位线耦合到沟道层的另一侧的端部，插入在沟道层的一侧的端部和源极线之间并且被配置为在其中掺杂有P型杂质的第一结，以及插入在端部之间的第二结的沟道层的另一侧和位线，并且被配置为在其中掺杂有N型杂质。

10. 发明授权

US08350309B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08350309B2
公开(公告)日：2013-01-08
申请号：US13310148
申请日：2011-12-02
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L27/108 , H01L29/73
CPC分类号： G11C16/0483 , G11C16/10
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

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