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1. 发明授权

US08627245B1 Density balancing in multiple patterning lithography using integrated circuit layout fill 有权
标题翻译：使用集成电路布局填充的多重图案化光刻中的密度平衡
公开(公告)号：US08627245B1
公开(公告)日：2014-01-07
申请号：US13596140
申请日：2012-08-28
申请人： Shayak Banerjee , Lars W. Liebmann , Ian P. Stobert
发明人： Shayak Banerjee , Lars W. Liebmann , Ian P. Stobert
IPC分类号： G06F17/50
CPC分类号： G03F7/70466 , G03F7/70433
摘要： In various embodiments, a method of designing an integrated circuit (IC) layout for a multiple patterning layout fill process includes: providing a pre-characterized mask tile library including a plurality of distinct mask tiles each having a distinct mask density on a plurality of distinct exposures each associated with a patterning process in the multiple patterning process; determining a density of a mask group in a first layout window in the IC layout, the first layout window including an open space unfilled by the mask group; and selecting a set of mask tiles from the plurality of distinct mask tiles to fill a portion of the open space, the selecting based upon the determined density of the mask group in the first layout window and the distinct mask density of the selected set of mask tiles on the plurality of distinct exposures.
摘要翻译：在各种实施例中，设计用于多图案化布局填充处理的集成电路（IC）布局的方法包括：提供预先表征的掩模片库，其包括多个不同的掩模片，每个掩模片在多个不同的图案布局填充处理中具有不同的掩模密度在多个图案化工艺中每个与图案化工艺相关联的曝光; 确定所述IC布局中的第一布局窗口中的掩模组的密度，所述第一布局窗口包括未被所述掩模组填充的开放空间; 以及从所述多个不同的掩模块中选择一组掩模块以填充所述开放空间的一部分，所述选择基于所述第一布局窗口中所确定的所述掩模组的密度和所选择的掩模组的所述不同掩模密度多个不同曝光的瓦片。

2. 发明授权

US08647893B1 Method for post decomposition density balancing in integrated circuit layouts, related system and program product 有权
标题翻译：集成电路布局中后分解密度平衡的方法，相关系统和程序产品
公开(公告)号：US08647893B1
公开(公告)日：2014-02-11
申请号：US13596126
申请日：2012-08-28
申请人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , G05B19/41835 , G06F17/5081 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.
摘要翻译：本发明的实施例提供了一种修改分解的集成电路（IC）布局的方法。该方法包括提供分解的IC布局，分解的IC布局包括一组颜色; 确定分解的IC布局中的每种颜色的浓度，其中每种颜色包括通过相关曝光形成的多个特征; 将分解的IC布局分离成一组瓦片; 确定所述瓦片组中的一个瓦片中具有最小密度的第一颜色和具有瓦片中最大密度的第二颜色，所述第一颜色包括第一组第一特征，所述第二颜色包括第一组第二特征; 以及用第二组第一特征替换所述瓦片上的所述第一组第二特征，以及所述瓦片上的所述第一组第一特征具有第二组第二特征。

3. 发明申请

US20140065728A1 METHOD FOR POST DECOMPOSITION DENSITY BALANCING IN INTEGRATED CIRCUIT LAYOUTS, RELATED SYSTEM AND PROGRAM PRODUCT 有权
标题翻译：一体化电路中分解密度平衡的方法，相关系统和程序产品
公开(公告)号：US20140065728A1
公开(公告)日：2014-03-06
申请号：US13596126
申请日：2012-08-28
申请人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
IPC分类号： H01L21/66 , G05B19/418
CPC分类号： H01L22/12 , G05B19/41835 , G06F17/5081 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.
摘要翻译：本发明的实施例提供了一种修改分解的集成电路（IC）布局的方法。该方法包括提供分解的IC布局，分解的IC布局包括一组颜色; 确定分解的IC布局中的每种颜色的浓度，其中每种颜色包括通过相关曝光形成的多个特征; 将分解的IC布局分离成一组瓦片; 确定所述瓦片组中的一个瓦片中具有最小密度的第一颜色和具有瓦片中最大密度的第二颜色，所述第一颜色包括第一组第一特征，所述第二颜色包括第一组第二特征; 以及用第二组第一特征替换所述瓦片上的所述第一组第二特征，以及所述瓦片上的所述第一组第一特征具有第二组第二特征。

4. 发明授权

US08103983B2 Electrically-driven optical proximity correction to compensate for non-optical effects 有权
标题翻译：电动光学接近校正补偿非光学效果
公开(公告)号：US08103983B2
公开(公告)日：2012-01-24
申请号：US12269477
申请日：2008-11-12
申请人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/10
摘要： A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.
摘要翻译：改进了用于集成电路的掩模设计的轮廓，以补偿由非光学效应（例如应力，阱接近度，快速热退火或间隔物厚度）引起的系统变化。提取使用掩模设计制造的模拟集成电路芯片的电气特性，并将其与设计规范进行比较，并调整轮廓的一个或多个边缘以减少系统变化，直到电气特性在规格范围内。特定的电特性优选地取决于由掩模制成的层：多晶硅的导通电流; 接触阻力; 金属电阻和电容; 当前活跃; 和通孔阻力。对于系统阈值电压变化，调整轮廓以根据芯片的标称阈值电压下的轮廓电流和栅极长度的预先计算的曲线来匹配对应于导通电流值的栅极长度。

5. 发明申请

US20100122231A1 ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS 有权
标题翻译：电动驱动光学近似校正补偿非光学效应
公开(公告)号：US20100122231A1
公开(公告)日：2010-05-13
申请号：US12269477
申请日：2008-11-12
申请人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/10
摘要： A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.
摘要翻译：改进了用于集成电路的掩模设计的轮廓，以补偿由非光学效应（例如应力，阱接近度，快速热退火或间隔物厚度）引起的系统变化。提取使用掩模设计制造的模拟集成电路芯片的电气特性，并将其与设计规范进行比较，并调整轮廓的一个或多个边缘以减少系统变化，直到电气特性在规格范围内。特定的电特性优选地取决于由掩模制成的层：多晶硅的导通电流; 接触阻力; 金属电阻和电容; 当前活跃; 和通孔阻力。对于系统阈值电压变化，调整轮廓以根据芯片的标称阈值电压下的轮廓电流和栅极长度的预先计算的曲线来匹配对应于导通电流值的栅极长度。

6. 发明授权

US07865864B2 Electrically driven optical proximity correction 有权
标题翻译：电驱动光学邻近校正
公开(公告)号：US07865864B2
公开(公告)日：2011-01-04
申请号：US12024188
申请日：2008-02-01
申请人： Shayak Banerjee , James A. Culp , Praveen Elakkumanan , Lars W. Liebmann
发明人： Shayak Banerjee , James A. Culp , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.
摘要翻译：描述了提供电驱动光学邻近校正的方法。在一个实施例中，存在执行电驱动光学邻近校正的方法。在本实施例中，接收表示由特征和边缘定义的多个分层形状的集成电路掩模布局。在掩模布局上运行光刻仿真。从掩模布局的每层的光刻模拟的输出中提取电特性。确定提取的电特性是否与目标电特性一致。响应于确定提取的掩模布局中的层的电特性不符合目标电特性，调整掩模布局中的多个分层形状的边缘。

7. 发明申请

US20090199151A1 ELECTRICALLY DRIVEN OPTICAL PROXIMITY CORRECTION 有权
标题翻译：电动驱动光学临近校正
公开(公告)号：US20090199151A1
公开(公告)日：2009-08-06
申请号：US12024188
申请日：2008-02-01
申请人： Shayak Banerjee , James A. Culp , Praveen Elakkumanan , Lars W. Liebmann
发明人： Shayak Banerjee , James A. Culp , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.
摘要翻译：描述了提供电驱动光学邻近校正的方法。在一个实施例中，存在执行电驱动光学邻近校正的方法。在本实施例中，接收表示由特征和边缘定义的多个分层形状的集成电路掩模布局。在掩模布局上运行光刻仿真。从掩模布局的每层的光刻模拟的输出中提取电特性。确定提取的电特性是否与目标电特性一致。响应于确定提取的掩模布局中的层的电特性不符合目标电特性，调整掩模布局中的多个分层形状的边缘。

8. 外观设计

USD829112S1 Sensing device 有权
公开(公告)号：USD829112S1
公开(公告)日：2018-09-25
申请号：US29575549
申请日：2016-08-25
申请人： Emmanuel Dumont , Shayak Banerjee , Mauricio Contreras
设计人： Emmanuel Dumont , Shayak Banerjee , Mauricio Contreras

9. 发明授权

US08782573B2 Solutions for retargeting integrated circuit layouts based on diffraction pattern analysis 失效
$Solutions for retargeting integrated circuit layouts based on diffraction pattern analysis$
标题翻译：基于衍射图案分析的重新定位集成电路布局的解决方案
公开(公告)号：US08782573B2
公开(公告)日：2014-07-15
申请号：US13600319
申请日：2012-08-31
申请人： Kanak B. Agarwal , Shayak Banerjee
发明人： Kanak B. Agarwal , Shayak Banerjee
IPC分类号： G06F17/50
CPC分类号： G03F7/70441
摘要： A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a set of diffraction-orders, the IC layout including a set of features defined by a set of target edges, analyzing the diffraction pattern with a merit function to estimate printability of the IC layout, monitoring a change in value of the merit function as a position of at least one of the set of target edges is adjusted across a range, and retargeting the set of target edges based on the monitoring of the merit function.
摘要翻译：公开了一种用于重新定位集成电路（IC）布局的计算机实现的方法。在一个实施例中，该方法包括生成包括一组衍射级的IC布局的衍射图案，该IC布局包括由一组目标边缘定义的一组特征，用优点函数分析衍射图案以估计可印刷性的IC布局，监视优值函数的值的变化作为所述一组目标边缘中的至少一个的位置在一个范围内被调整，并且基于所述优值函数的监视来重新定位所述一组目标边缘。

10. 发明授权

US08464194B1 Machine learning approach to correct lithographic hot-spots 失效
标题翻译：机器学习方法来纠正光刻热点
公开(公告)号：US08464194B1
公开(公告)日：2013-06-11
申请号：US13328994
申请日：2011-12-16
申请人： Kanak Behari Agarwal , Shayak Banerjee
发明人： Kanak Behari Agarwal , Shayak Banerjee
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/70433
摘要： A method, system, and computer program product for machine learning approach for detecting and correcting lithographic hot-spots in an integrated circuit (IC) design are provided in the illustrative embodiments. A layout corresponding to the IC design is received at a machine learning model (ML model). At the ML model using a hardware component, a set of input objects is identified corresponding to a target shape in the layout. A retargeting value is predicted for the target shape using the set of input objects, such that applying the retargeting value to the target shape in the layout causes the target shape to be modified into a modified target shape, wherein printing the modified target shape instead of the target shape eliminates a lithographic hot-spot that would otherwise occur from printing the target shape in a printed circuit corresponding to the IC design.
摘要翻译：在说明性实施例中提供了用于在集成电路（IC）设计中检测和校正平版印刷热点的用于机器学习方法的方法，系统和计算机程序产品。在机器学习模型（ML模型）下接收与IC设计相对应的布局。在使用硬件组件的ML模型中，在布局中识别与目标形状相对应的一组输入对象。使用所述一组输入对象来对目标形状预测重定向值，使得将重定向值应用于布局中的目标形状使得目标形状被修改为修改的目标形状，其中，打印修改的目标形状而不是目标形状消除了在对应于IC设计的印刷电路中打印目标形状否则会发生的平版印刷热点。

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