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1. 发明授权

US08627245B1 Density balancing in multiple patterning lithography using integrated circuit layout fill 有权
标题翻译：使用集成电路布局填充的多重图案化光刻中的密度平衡
公开(公告)号：US08627245B1
公开(公告)日：2014-01-07
申请号：US13596140
申请日：2012-08-28
申请人： Shayak Banerjee , Lars W. Liebmann , Ian P. Stobert
发明人： Shayak Banerjee , Lars W. Liebmann , Ian P. Stobert
IPC分类号： G06F17/50
CPC分类号： G03F7/70466 , G03F7/70433
摘要： In various embodiments, a method of designing an integrated circuit (IC) layout for a multiple patterning layout fill process includes: providing a pre-characterized mask tile library including a plurality of distinct mask tiles each having a distinct mask density on a plurality of distinct exposures each associated with a patterning process in the multiple patterning process; determining a density of a mask group in a first layout window in the IC layout, the first layout window including an open space unfilled by the mask group; and selecting a set of mask tiles from the plurality of distinct mask tiles to fill a portion of the open space, the selecting based upon the determined density of the mask group in the first layout window and the distinct mask density of the selected set of mask tiles on the plurality of distinct exposures.
摘要翻译：在各种实施例中，设计用于多图案化布局填充处理的集成电路（IC）布局的方法包括：提供预先表征的掩模片库，其包括多个不同的掩模片，每个掩模片在多个不同的图案布局填充处理中具有不同的掩模密度在多个图案化工艺中每个与图案化工艺相关联的曝光; 确定所述IC布局中的第一布局窗口中的掩模组的密度，所述第一布局窗口包括未被所述掩模组填充的开放空间; 以及从所述多个不同的掩模块中选择一组掩模块以填充所述开放空间的一部分，所述选择基于所述第一布局窗口中所确定的所述掩模组的密度和所选择的掩模组的所述不同掩模密度多个不同曝光的瓦片。

2. 发明申请

US20140065728A1 METHOD FOR POST DECOMPOSITION DENSITY BALANCING IN INTEGRATED CIRCUIT LAYOUTS, RELATED SYSTEM AND PROGRAM PRODUCT 有权
标题翻译：一体化电路中分解密度平衡的方法，相关系统和程序产品
公开(公告)号：US20140065728A1
公开(公告)日：2014-03-06
申请号：US13596126
申请日：2012-08-28
申请人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
IPC分类号： H01L21/66 , G05B19/418
CPC分类号： H01L22/12 , G05B19/41835 , G06F17/5081 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.
摘要翻译：本发明的实施例提供了一种修改分解的集成电路（IC）布局的方法。该方法包括提供分解的IC布局，分解的IC布局包括一组颜色; 确定分解的IC布局中的每种颜色的浓度，其中每种颜色包括通过相关曝光形成的多个特征; 将分解的IC布局分离成一组瓦片; 确定所述瓦片组中的一个瓦片中具有最小密度的第一颜色和具有瓦片中最大密度的第二颜色，所述第一颜色包括第一组第一特征，所述第二颜色包括第一组第二特征; 以及用第二组第一特征替换所述瓦片上的所述第一组第二特征，以及所述瓦片上的所述第一组第一特征具有第二组第二特征。

3. 发明授权

US08647893B1 Method for post decomposition density balancing in integrated circuit layouts, related system and program product 有权
标题翻译：集成电路布局中后分解密度平衡的方法，相关系统和程序产品
公开(公告)号：US08647893B1
公开(公告)日：2014-02-11
申请号：US13596126
申请日：2012-08-28
申请人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , G05B19/41835 , G06F17/5081 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.
摘要翻译：本发明的实施例提供了一种修改分解的集成电路（IC）布局的方法。该方法包括提供分解的IC布局，分解的IC布局包括一组颜色; 确定分解的IC布局中的每种颜色的浓度，其中每种颜色包括通过相关曝光形成的多个特征; 将分解的IC布局分离成一组瓦片; 确定所述瓦片组中的一个瓦片中具有最小密度的第一颜色和具有瓦片中最大密度的第二颜色，所述第一颜色包括第一组第一特征，所述第二颜色包括第一组第二特征; 以及用第二组第一特征替换所述瓦片上的所述第一组第二特征，以及所述瓦片上的所述第一组第一特征具有第二组第二特征。

4. 发明授权

US08103983B2 Electrically-driven optical proximity correction to compensate for non-optical effects 有权
标题翻译：电动光学接近校正补偿非光学效果
公开(公告)号：US08103983B2
公开(公告)日：2012-01-24
申请号：US12269477
申请日：2008-11-12
申请人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/10
摘要： A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.
摘要翻译：改进了用于集成电路的掩模设计的轮廓，以补偿由非光学效应（例如应力，阱接近度，快速热退火或间隔物厚度）引起的系统变化。提取使用掩模设计制造的模拟集成电路芯片的电气特性，并将其与设计规范进行比较，并调整轮廓的一个或多个边缘以减少系统变化，直到电气特性在规格范围内。特定的电特性优选地取决于由掩模制成的层：多晶硅的导通电流; 接触阻力; 金属电阻和电容; 当前活跃; 和通孔阻力。对于系统阈值电压变化，调整轮廓以根据芯片的标称阈值电压下的轮廓电流和栅极长度的预先计算的曲线来匹配对应于导通电流值的栅极长度。

5. 发明申请

US20100122231A1 ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS 有权
标题翻译：电动驱动光学近似校正补偿非光学效应
公开(公告)号：US20100122231A1
公开(公告)日：2010-05-13
申请号：US12269477
申请日：2008-11-12
申请人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/10
摘要： A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.
摘要翻译：改进了用于集成电路的掩模设计的轮廓，以补偿由非光学效应（例如应力，阱接近度，快速热退火或间隔物厚度）引起的系统变化。提取使用掩模设计制造的模拟集成电路芯片的电气特性，并将其与设计规范进行比较，并调整轮廓的一个或多个边缘以减少系统变化，直到电气特性在规格范围内。特定的电特性优选地取决于由掩模制成的层：多晶硅的导通电流; 接触阻力; 金属电阻和电容; 当前活跃; 和通孔阻力。对于系统阈值电压变化，调整轮廓以根据芯片的标称阈值电压下的轮廓电流和栅极长度的预先计算的曲线来匹配对应于导通电流值的栅极长度。

6. 发明授权

US07865864B2 Electrically driven optical proximity correction 有权
标题翻译：电驱动光学邻近校正
公开(公告)号：US07865864B2
公开(公告)日：2011-01-04
申请号：US12024188
申请日：2008-02-01
申请人： Shayak Banerjee , James A. Culp , Praveen Elakkumanan , Lars W. Liebmann
发明人： Shayak Banerjee , James A. Culp , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.
摘要翻译：描述了提供电驱动光学邻近校正的方法。在一个实施例中，存在执行电驱动光学邻近校正的方法。在本实施例中，接收表示由特征和边缘定义的多个分层形状的集成电路掩模布局。在掩模布局上运行光刻仿真。从掩模布局的每层的光刻模拟的输出中提取电特性。确定提取的电特性是否与目标电特性一致。响应于确定提取的掩模布局中的层的电特性不符合目标电特性，调整掩模布局中的多个分层形状的边缘。

7. 发明申请

US20090199151A1 ELECTRICALLY DRIVEN OPTICAL PROXIMITY CORRECTION 有权
标题翻译：电动驱动光学临近校正
公开(公告)号：US20090199151A1
公开(公告)日：2009-08-06
申请号：US12024188
申请日：2008-02-01
申请人： Shayak Banerjee , James A. Culp , Praveen Elakkumanan , Lars W. Liebmann
发明人： Shayak Banerjee , James A. Culp , Praveen Elakkumanan , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.
摘要翻译：描述了提供电驱动光学邻近校正的方法。在一个实施例中，存在执行电驱动光学邻近校正的方法。在本实施例中，接收表示由特征和边缘定义的多个分层形状的集成电路掩模布局。在掩模布局上运行光刻仿真。从掩模布局的每层的光刻模拟的输出中提取电特性。确定提取的电特性是否与目标电特性一致。响应于确定提取的掩模布局中的层的电特性不符合目标电特性，调整掩模布局中的多个分层形状的边缘。

8. 发明授权

US08516403B2 Multiple patterning layout decomposition for ease of conflict removal 有权
标题翻译：多重图案化布局分解，便于冲突删除
公开(公告)号：US08516403B2
公开(公告)日：2013-08-20
申请号：US13223844
申请日：2011-09-01
申请人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction. The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features. The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors.
摘要翻译：提供了一种用于具有冲突消除意识着色的多重图案化光刻的机构。该机制使得多个图案化着色意识到冲突移除开销。着色解决方案明确地将冲突移除的容易性作为着色目标之一。该机制预先计算出每个方向上可以移动多少形状。该机制生成一个冲突图，其中节点表示布局中的形状，边缘表示形状之间的冲突。该机制基于冲突特征之间的可用空间松弛来为边缘分配权重。该机构然后使用重量来引导多个图案化着色。该机制优先处理具有较高权重的冲突特征，以分配不同的颜色。

9. 发明授权

US08473885B2 Physical design system and method 失效
公开(公告)号：US08473885B2
公开(公告)日：2013-06-25
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

10. 发明授权

US08225255B2 Placement and optimization of process dummy cells 有权
标题翻译：过程虚拟细胞的放置和优化
公开(公告)号：US08225255B2
公开(公告)日：2012-07-17
申请号：US12124472
申请日：2008-05-21
申请人： Xu Ouyang , Geng Han , Lars W. Liebmann
发明人： Xu Ouyang , Geng Han , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G11C29/24 , G06F2217/12 , G11C5/02 , H01L27/0203 , H01L27/105 , Y02P90/265
摘要： A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.
摘要翻译：与存储器阵列的内部存储单元相关地布置处理虚设单元的方法包括：（a）计算存储器阵列的初始处理性能参数; （b）改变电连接到内部单元的层的虚拟单元布局配置; （c）为内部存储单元和改变的布局配置处理虚拟单元应用光刻模拟和屈服模型; 和（d）重复步骤（b）和（c），直到产率最大化。可以进行检查，以确保有足够的空间进行更改，并且对相邻电路没有明显的不利影响。过程性能参数可以是产量或内部存储器单元的处理窗口。

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