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    • 10. 发明授权
    • Method for fabricating planar semiconductor wafers
    • 制造平面半导体晶圆的方法
    • US07179736B2
    • 2007-02-20
    • US10966074
    • 2004-10-14
    • Byung-Sung Leo KwakPeter BurkeSey-Shing Sun
    • Byung-Sung Leo KwakPeter BurkeSey-Shing Sun
    • H01L21/4763
    • H01L21/76877C25D5/18C25D7/123H01L21/2885H01L21/7684
    • The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is next place in a plating bath that includes an accelerator, which tends to collect in the vias and trenches to accelerate the rate of plating in these areas relative to the planar regions of the wafer. After the gapfill point is reached, the plating is stopped by removing the plating bias on wafer. An equilibrium period is then introduced into the process, allowing higher concentrations of accelerator additives and other components of the bath)] above the via and trench regions to equilibrate in the plating bath. The bulk plating on the wafer is resumed after equilibration. Over-plating on the wafer in the areas of the vias and trenches is therefore avoided, resulting in a more planar metallization layer on the wafer, without the use of a leveler additive which adversely affects the gapfill capability.
    • 本发明涉及一种制造平面半导体晶片的方法。 该方法包括在半导体晶片表面上形成电介质层,该半导体晶片表面具有通孔,沟槽和平面区域。 然后在电介质层上形成阻挡层和种子金属层。 晶片是包含加速器的镀液中的下一个位置,该加速器倾向于在通路和沟槽中收集,以加速相对于晶片的平面区域在这些区域中的电镀速率。 达到间隙填充点后,通过去除晶片上的电镀偏压来停止电镀。 然后在该过程中引入平衡时段,允许较高浓度的促进剂添加剂和浴中的其它组分)]在通孔和沟槽区域上方在电镀浴中平衡。 平衡后恢复晶片上的块体电镀。 因此避免了在通孔和沟槽区域上的晶片上的过电镀,导致晶片上更平面的金属化层,而不使用不利地影响间隙填充能力的矫直添加剂。