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1. 发明申请

US20110233684A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110233684A1
公开(公告)日：2011-09-29
申请号：US13049540
申请日：2011-03-16
申请人： Kenichi MATSUSHITA
发明人： Kenichi MATSUSHITA
IPC分类号： H01L29/739
CPC分类号： H01L27/0623 , H01L29/1095 , H01L29/7397
摘要： According to one embodiment, a semiconductor device includes a first main electrode, a base layer of a first conductivity type, a barrier layer of the first conductivity type, a diffusion layer of a second conductivity type, a base layer of the second conductivity type, a first conductor layer, a second conductor layer, and a second main electrode. The base layer of the first conductivity type is provided on the first main electrode. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are provided on the base layer of the first conductivity type. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are arranged alternately. The base layer of the second conductivity type is provided on the barrier layer of the first conductivity type. The first conductor layer and the second conductor layer are provided between the base layer of the second conductivity type and the diffusion layer of the second conductivity type and between the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type. The first conductor layer and the second conductor layer are provided with trench configurations with an interposed insulating film. The second main electrode is connected to the base layer of the second conductivity type. Bottom faces of the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are positioned on the first main electrode side of lower ends of the first conductor layer and the second conductor layer. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type form a super junction proximally to tips of the first conductor layer and the second conductor layer.
摘要翻译：根据一个实施例，半导体器件包括第一主电极，第一导电类型的基极层，第一导电类型的势垒层，第二导电类型的扩散层，第二导电类型的基极层，第一导体层，第二导体层和第二主电极。第一导电类型的基层设置在第一主电极上。第一导电类型的阻挡层和第二导电类型的扩散层设置在第一导电类型的基极层上。第一导电类型的阻挡层和第二导电类型的扩散层交替布置。第二导电类型的基层设置在第一导电类型的阻挡层上。第一导体层和第二导体层设置在第二导电类型的基极层和第二导电类型的扩散层之间以及第一导电类型的阻挡层与第二导电类型的扩散层之间。第一导体层和第二导体层设置有具有插入的绝缘膜的沟槽构造。第二主电极连接到第二导电类型的基极层。第一导电类型的阻挡层的底面和第二导电类型的扩散层位于第一导体层和第二导体层的下端的第一主电极侧。第一导电类型的阻挡层和第二导电类型的扩散层形成与第一导体层和第二导体层的尖端近端的超级结。

2. 发明授权

US07633153B2 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US07633153B2
公开(公告)日：2009-12-15
申请号：US11778516
申请日：2007-07-16
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H01L23/10
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.
摘要翻译：半导体模块包括安装板。多个电源开关器件芯片通过倒装芯片接合安装在安装板上。芯片具有上表面和下表面，并且被配置为面向安装板的上表面。通过倒装芯片接合将驱动IC芯片安装在安装板上。驱动IC芯片用于驱动形成在多个功率开关器件芯片中的晶体管的栅极。多个散热构件分别位于多个功率开关器件芯片的下表面上。提供树脂构件以将单个封装中的多个功率开关器件芯片和驱动IC芯片密封。

3. 发明申请

US20090128279A1 INTEGRATED CIRCUIT DEVICE 失效
标题翻译：集成电路设备
公开(公告)号：US20090128279A1
公开(公告)日：2009-05-21
申请号：US12269396
申请日：2008-11-12
申请人： Kenichi Matsushita , Ichiro Omura
发明人： Kenichi Matsushita , Ichiro Omura
IPC分类号： G05F1/00 , H01F27/28
CPC分类号： H01F17/0033 , H01F27/402 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes: a main interconnect; and a coil located on one side of the main interconnect at a position fixed with respect to the main interconnect, the coil having a central axis extending in a direction crossing the extending direction of the main interconnect. An induction current detectable by the coil is generated due to a current flowing through the main interconnect.
摘要翻译：集成电路装置包括：主互连; 以及位于所述主互连的一侧上的线圈，所述线圈相对于所述主互连固定，所述线圈具有沿与所述主互连的延伸方向交叉的方向延伸的中心轴线。由于电流流过主互连线，可以产生由线圈检测到的感应电流。

4. 发明授权

US07531876B2 Semiconductor device having power semiconductor elements 失效
标题翻译：具有功率半导体元件的半导体器件
公开(公告)号：US07531876B2
公开(公告)日：2009-05-12
申请号：US11230624
申请日：2005-09-21
申请人： Ichiro Omura , Kenji Takahashi , Chiaki Takubo , Hideo Aoki , Hideo Numata , Mie Matsuo , Hirokazu Ezawa , Susumu Harada , Hisashi Kaneko , Hiroshi Ikenoue , Kenichi Matsushita
发明人： Ichiro Omura , Kenji Takahashi , Chiaki Takubo , Hideo Aoki , Hideo Numata , Mie Matsuo , Hirokazu Ezawa , Susumu Harada , Hisashi Kaneko , Hiroshi Ikenoue , Kenichi Matsushita
IPC分类号： H01L23/62
CPC分类号： H01L29/41766 , H01L23/481 , H01L24/14 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L29/7809 , H01L29/7811 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/30107 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/05005 , H01L2224/05541 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.
摘要翻译：提供了一种尺寸小型化，电流通路电阻低，寄生电感小，可靠性优异的半导体装置。该半导体器件包括半导体衬底，形成在半导体衬底的前表面上的第一主电极，形成在半导体衬底的后表面上的第二主电极和形成在半导体衬底的背面上的导电部分穿过半导体衬底，其中第二主电极经由导电部分被提取到半导体衬底的前表面。并且，导电部是贯通通孔，该通孔在其厚度方向上形成有通过半导体基板的通孔，以及形成在通孔中并连接到第二主电极的导电部。

5. 发明申请

US20080251838A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080251838A1
公开(公告)日：2008-10-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
摘要翻译：半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上，以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。

6. 发明申请

US20070034894A1 Semiconductor device including field effect transistor for use as a high-speed switching device and a power device 失效
标题翻译：包括用作高速开关装置的场效应晶体管和功率器件的半导体装置
公开(公告)号：US20070034894A1
公开(公告)日：2007-02-15
申请号：US11501715
申请日：2006-08-10
申请人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
发明人： Yusuke Kawaguchi , Norio Yasuhara , Tomoko Matsudai , Kenichi Matsushita
IPC分类号： H01L29/74
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译：在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。在栅极绝缘膜上形成栅电极。偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

7. 发明授权

US5883402A Semiconductor device and protection method 失效
标题翻译：半导体器件及保护方法
公开(公告)号：US5883402A
公开(公告)日：1999-03-16
申请号：US744245
申请日：1996-11-05
申请人： Ichiro Omura , Tsuneo Ogura , Kenichi Matsushita , Hideaki Ninomiya
发明人： Ichiro Omura , Tsuneo Ogura , Kenichi Matsushita , Hideaki Ninomiya
IPC分类号： H01L27/02 , H01L29/74
CPC分类号： H01L27/0248 , H01L2924/0002
摘要： A semiconductor device comprises a main switching element, an electric field detector and an on-voltage application unit. The main switching element includes a high-voltage main electrode, at least a low-voltage main electrode and at least a first gate electrode. The electric field detector has a MOS structure making conductive between the high-voltage main electrode and the first gate electrode in a path other than the main switching element in accordance with a predetermined electric field generated in the main switching element. The on-voltage application unit applies an on-voltage to the first gate electrode on the basis of the conductive state.
摘要翻译：半导体器件包括主开关元件，电场检测器和导通电压施加单元。主开关元件包括高压主电极，至少低电压主电极和至少第一栅电极。电场检测器根据主开关元件中产生的预定电场，在主开关元件以外的路径中，在高电压主电极与第一栅电极之间导通MOS结构。导通电压单元基于导通状态对第一栅电极施加导通电压。

8. 发明授权

US07864021B2 Integrated circuit device 失效
标题翻译：集成电路器件
公开(公告)号：US07864021B2
公开(公告)日：2011-01-04
申请号：US12269396
申请日：2008-11-12
申请人： Kenichi Matsushita , Ichiro Omura
发明人： Kenichi Matsushita , Ichiro Omura
IPC分类号： H01F27/28 , H01F5/00 , G05F1/00
CPC分类号： H01F17/0033 , H01F27/402 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes: a main interconnect; and a coil located on one side of the main interconnect at a position fixed with respect to the main interconnect, the coil having a central axis extending in a direction crossing the extending direction of the main interconnect. An induction current detectable by the coil is generated due to a current flowing through the main interconnect.
摘要翻译：集成电路装置包括：主互连; 以及位于所述主互连的一侧上的线圈，所述线圈相对于所述主互连固定，所述线圈具有沿与所述主互连的延伸方向交叉的方向延伸的中心轴线。由于电流流过主互连线，可以产生由线圈检测到的感应电流。

9. 发明申请

US20100159659A1 SEMICONDUCTOR DEVICE USED AS HIGH-SPEED SWITCHING DEVICE AND POWER DEVICE 有权
标题翻译：用作高速切换装置和电源装置的半导体装置
公开(公告)号：US20100159659A1
公开(公告)日：2010-06-24
申请号：US12716352
申请日：2010-03-03
申请人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
发明人： Tomoko Matsudai , Norio Yasuhara , Yusuke Kawaguchi , Kenichi Matsushita
IPC分类号： H01L21/336
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译：在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。第一导电类型的源区形成在高电阻层的表面区域上。第一导电类型的漏极区域形成在与源极区域一定距离处。在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

10. 发明授权

US07663186B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07663186B2
公开(公告)日：2010-02-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a substrate, a surface portion thereof serving as a drain layer; a first main electrode connected to the drain layer; an epitaxial layer formed on the drain layer; a base layer formed on the epitaxial layer; a source layer formed in a base layer surface portion; an insulated trench sandwiched by base layers; a JFET layer formed on trench side walls; an LDD layer formed in a base layer surface portion and connected to the JFET layer around a top face of the trench; a control electrode formed on a gate insulating film formed on an LDD layer surface part, on surfaces of source layer end parts facing each other across the trench, and on a base layer region sandwiched by the LDD and source layers; and a second main electrode connected to the source and base layers sandwiching the control electrode.
摘要翻译：半导体器件包括：衬底，用作漏极层的表面部分; 连接到漏极层的第一主电极; 形成在漏极层上的外延层; 形成在外延层上的基底层; 形成在基层表面部分中的源极层; 由基层夹住的绝缘沟槽; 形成在沟槽侧壁上的JFET层; LDD层，其形成在基底表面部分中并且围绕所述沟槽的顶面连接到所述JFET层; 形成在形成在LDD层表面部分上的栅极绝缘膜上的控制电极，在沟槽之间彼此面对的源极层部分的表面上以及由LDD和源极层夹持的基极层区域; 以及连接到夹持控制电极的源极和基极层的第二主电极。

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