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    • 9. 发明授权
    • Image processing apparatus
    • 图像处理装置
    • US07113655B2
    • 2006-09-26
    • US10366465
    • 2003-02-14
    • Atsushi Narita
    • Atsushi Narita
    • G06K9/60H02H3/05H04N5/14
    • G09G5/393G09G2340/10
    • An image processing apparatus enabling alpha blending or other image processing during bit block transfer (bitblt), wherein the selector 52 selects one of the primitive data S143, the image data S12 and the image data S147a that are used for the host-local transfer, and outputs the data to the alpha blend circuit 53. According to the control signal S55, the alpha blend circuit 53 turns on or turns off alpha blending. The selector 54 selects either the image data S139 or the image data S53 and writes the data to the DRAM 147.
    • 一种图像处理装置,在位块传送(bitblt)期间能够进行α混合或其他图像处理,其中选择器52选择用于主机的原始数据S 143,图像数据S 12和图像数据S 147a之一 - 局部传送,并将该数据输出到阿尔法混合电路53。 根据控制信号S 55,阿尔法混合电路53打开或关闭α混合。 选择器54选择图像数据S 139或图像数据S 53,并将数据写入DRAM147。
    • 10. 发明授权
    • Image processing apparatus
    • 图像处理装置
    • US07068279B2
    • 2006-06-27
    • US10161738
    • 2002-06-05
    • Atsushi Narita
    • Atsushi Narita
    • G06T1/60
    • G11C11/40618G11C11/406G11C2207/104
    • An image processing apparatus capable of performing a refresh operation without causing a drop in performance, an increase in cost, or damage to the apparatus. The apparatus further being capable of achieving a reduction in power consumption, and being provided with a memory I/F circuit able to not only refresh, for example, four DRAM modules simultaneously, but also capable of refreshing two DRAM modules at a same timing, then refreshing the remaining two DRAM modules simultaneously at a next timing, or refreshing the four DRAM modules one by one in order based on given refresh control data, and controlling the timing of the refresh operation for each divided DRAM module.
    • 一种能够执行刷新操作而不会导致性能下降,成本增加或对设备的损坏的图像处理设备。 该装置还能够实现功率消耗的降低,并且设置有能够同时刷新例如四个DRAM模块,而且能够以相同的定时刷新两个DRAM模块的存储器I / F电路, 然后在下一个定时同时刷新剩余的两个DRAM模块,或者基于给定的刷新控制数据逐个刷新四个DRAM模块,并且控制每个划分的DRAM模块的刷新操作的定时。