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1. 发明授权

US08754471B2 Semiconductor device having gate in recess 有权
标题翻译：半导体器件具有凹槽中的栅极
公开(公告)号：US08754471B2
公开(公告)日：2014-06-17
申请号：US13040610
申请日：2011-03-04
申请人： Toshiaki Iwamatsu , Kozo Ishikawa , Masashi Kitazawa , Kiyoshi Hayashi , Takahiro Maruyama , Masaaki Shinohara , Kenji Kawai
发明人： Toshiaki Iwamatsu , Kozo Ishikawa , Masashi Kitazawa , Kiyoshi Hayashi , Takahiro Maruyama , Masaaki Shinohara , Kenji Kawai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66621 , H01L21/28 , H01L29/66795 , H01L29/772 , H01L29/7834 , Y02E10/50
摘要： There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.
摘要翻译：提供了可以在不劣化特性的情况下小型化的半导体器件及其制造方法。半导体器件包括：主表面，源极区域和漏极区域在主表面彼此分离形成的半导体衬底;形成在源区域和漏极区域之间的主表面上的栅电极层;第一形成为与源极区域的表面接触的导电层，以及形成为与漏极区域的表面接触的第二导电层。在主表面上形成凹部，以便通过栅极电极层下面的部分从第一导电层和源极区域之间的接触区域延伸到第二导电层和漏极区域之间的接触区域。

2. 发明授权

US09287400B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US09287400B2
公开(公告)日：2016-03-15
申请号：US13587361
申请日：2012-08-16
申请人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
发明人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L21/265
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/28035 , H01L21/3081 , H01L21/3086 , H01L21/321 , H01L29/785
摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

3. 发明授权

US08269288B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08269288B2
公开(公告)日：2012-09-18
申请号：US12253563
申请日：2008-10-17
申请人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
发明人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
IPC分类号： H01L29/06
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/28035 , H01L21/3081 , H01L21/3086 , H01L21/321 , H01L29/785
摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.
摘要翻译：本发明的目的是提供一种半导体器件，其具有通过以高精度形成鳍状半导体部分和栅极电极或通过改善元件之间的特性变化而具有优异的特性的鳍型晶体管。本发明是一种半导体器件，包括：鳍状半导体部分，其一侧形成有源极区域，在其另一侧形成有漏极区域，以及形成在源极区域和漏极区域之间的栅电极，翅片状半导体部分，其间具有栅极绝缘膜。解决根据本发明的问题的一种解决方案是栅电极使用可湿蚀刻的金属材料或硅化物材料。

4. 发明申请

US20110031552A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110031552A1
公开(公告)日：2011-02-10
申请号：US12852039
申请日：2010-08-06
申请人： Toshiaki IWAMATSU , Kozo Ishikawa , Kiyoshi Hayashi
发明人： Toshiaki IWAMATSU , Kozo Ishikawa , Kiyoshi Hayashi
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/845 , H01L27/1211
摘要： To provide, in FINFET whose threshold voltage is determined essentially by the work function of a gate electrode, a technology capable of adjusting the threshold voltage of FINFET without changing the material of the gate electrode. FINFET is formed over an SOI substrate comprised of a substrate layer, a buried insulating layer formed over the substrate layer, and a silicon layer formed over the buried insulating layer. The substrate layer has therein a first semiconductor region contiguous to the buried insulating layer. The silicon layer of the SOI substrate is processed into a fin. A ratio of the height of the fin to the width of the fin is adjusted to fall within a range of from 1 or greater but not greater than 2. In addition, a voltage can be applied to the first semiconductor region.
摘要翻译：在FINFET中，其阈值电压基本上由栅电极的功函数确定，能够在不改变栅电极的材料的情况下调节FINFET的阈值电压的技术。 FINFET形成在由衬底层，在衬底层上形成的掩埋绝缘层和形成在掩埋绝缘层上的硅层的SOI衬底上。衬底层中具有与掩埋绝缘层邻接的第一半导体区域。将SOI衬底的硅层加工成翅片。将翅片的高度与翅片的宽度的比率调整为在1以上但不大于2的范围内。此外，可以向第一半导体区域施加电压。

5. 发明申请

US20090101977A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090101977A1
公开(公告)日：2009-04-23
申请号：US12253563
申请日：2008-10-17
申请人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
发明人： Toshiaki Iwamatsu , Takashi Terada , Hirofumi Shinohara , Kozo Ishikawa , Ryuta Tsuchiya , Kiyoshi Hayashi
IPC分类号： H01L47/00 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/28035 , H01L21/3081 , H01L21/3086 , H01L21/321 , H01L29/785
摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.
摘要翻译：本发明的目的是提供一种半导体器件，其具有通过以高精度形成鳍状半导体部分和栅极电极或通过改善元件之间的特性变化而具有优异的特性的鳍型晶体管。本发明是一种半导体器件，包括：鳍状半导体部分，其一侧形成有源极区域，在其另一侧形成有漏极区域，以及形成在源极区域和漏极区域之间的栅电极，翅片状半导体部分，其间具有栅极绝缘膜。解决根据本发明的问题的一种解决方案是栅电极使用可湿蚀刻的金属材料或硅化物材料。

6. 发明授权

US08308622B2 Centrifugally cast composit roll 有权
标题翻译：离心铸造复合辊
公开(公告)号：US08308622B2
公开(公告)日：2012-11-13
申请号：US12097953
申请日：2006-03-13
申请人： Kiyoshi Furushima , Shunji Matsumoto , Ryota Honda , Kiyoshi Hayashi , Takashi Honda , Masatsugu Uchida , Seiji Oyama , Takuya Osue
发明人： Kiyoshi Furushima , Shunji Matsumoto , Ryota Honda , Kiyoshi Hayashi , Takashi Honda , Masatsugu Uchida , Seiji Oyama , Takuya Osue
IPC分类号： F16C13/00 , B32B15/18
CPC分类号： B22D13/04 , B21B27/03 , B32B15/011 , C22C37/00 , C22C37/06 , C22C37/10 , C22C38/22 , C22C38/24 , Y10T428/12778 , Y10T428/12951 , Y10T428/12965 , Y10T428/12979
摘要： A centrifugally cast composite roll comprising an outer layer having a composition comprising by mass 2.5-9% of C, 0.1-3.5% of Si, 0.1-3.5% of Mn, and 11-40% of V, the balance being Fe and inevitable impurities; an intermediate layer made of a high-speed steel alloy, which is formed inside the outer layer; and an inner layer made of cast iron or steel, which is formed inside the intermediate layer.
摘要翻译：一种离心铸造复合辊，其包含外层，其组成包括质量为2.5-9％的C，0.1-3.5％的Si，0.1-3.5％的Mn和11-40％的V，余量为Fe和不可避免的杂质; 形成在外层内的由高速钢合金制成的中间层; 以及形成在中间层内的由铸铁或钢制成的内层。

7. 发明申请

US20070092792A1 ELECTRODE UNIT FOR PRISMATIC BATTERY, PRISMATIC BATTERY, AND METHOD OF MANUFACTURING ELECTRODE UNIT FOR PRISMATIC BATTERY 有权
标题翻译：用于静电电池的电极单元，静电电池和制造用于静电电池的电极单元的方法
公开(公告)号：US20070092792A1
公开(公告)日：2007-04-26
申请号：US11552695
申请日：2006-10-25
申请人： Hideki Kasahara , Kiyoshi Hayashi
发明人： Hideki Kasahara , Kiyoshi Hayashi
IPC分类号： H01M2/26 , H01M4/58 , H01M4/04
CPC分类号： H01M2/263 , H01M2/0217 , H01M10/0413 , H01M10/052 , H01M10/058 , H01M10/281 , H01M10/345 , Y10T29/49115
摘要： To provide an electrode unit for a prismatic battery capable of increasing the output of the battery while suppressing the battery internal resistance value and improving the degree of freedom of the size of the electrode plate. An electrode unit for a prismatic battery including an electrode group in which positive electrode plates and negative electrode plates in an almost rectangular shape are alternately stacked with separators interposed therebetween. In each of the positive electrode plate and the negative electrode plate, core material exposed portions are formed at least on two side edges. The positive electrode plates and the negative electrode plate are stacked such that their core material exposed portions are directed not to overlap each other in the stack direction. The electrode unit for a prismatic battery includes a positive current collector having a shape capable of joining to all of the core material exposed portions of the positive electrode plates constituting the electrode group, and a negative current collector capable of joining to all of the core material exposed portions of the negative electrode plates constituting the electrode group, not in contact with the positive current collector.
摘要翻译：为了提供能够增加电池输出的方形电池的电极单元，同时抑制电池内阻值并提高电极板尺寸的自由度。一种用于棱柱电池的电极单元，其包括其中正极板和大致矩形形状的负极板彼此交替堆叠的电极组，隔板之间交替堆叠。在正极板和负极板的每一个中，至少在两个侧边缘上形成有芯材料暴露部分。正极板和负极板堆叠成使得它们的芯材暴露部分在堆叠方向上不相互重叠。用于棱柱形电池的电极单元包括具有能够接合构成电极组的正极板的所有芯材暴露部分的形状的正极集电体，以及能够与所有芯材连接的负极集电体构成电极组的负极板的暴露部分不与正极集电体接触。

8. 发明授权

US5818761A Non-volatile semiconductor memory device capable of high speed programming/erasure 失效
标题翻译：能够高速编程/擦除的非易失性半导体存储器件
公开(公告)号：US5818761A
公开(公告)日：1998-10-06
申请号：US897101
申请日：1997-07-18
申请人： Takahiro Onakado , Hiroshi Takada , Kiyoshi Hayashi
发明人： Takahiro Onakado , Hiroshi Takada , Kiyoshi Hayashi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3486 , G11C16/0416 , G11C16/3468
摘要： To a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.
摘要翻译：对于连接所选存储单元的列线，通过具有与存储单元晶体管不同的沟道导电类型的选择栅极晶体管提供写偏置电压。选择栅极晶体管的电流驱动能力适于大于存储单元的泄漏电流，并且在一个方面形成通道时，提供小于沟道电流的电流。当对所选字线施加验证电压时，当形成通道时，大的通道电流流动，子行线的电位相应地改变，并且编程被抑制。在另一方面，选择栅晶体管用作恒流源，以使存储器单元的编程速度恒定。因此，可以使编程后的阈值分布变窄。

9. 发明授权

US5523622A Semiconductor integrated device having parallel signal lines 失效
标题翻译：具有并行信号线的半导体集成器件
公开(公告)号：US5523622A
公开(公告)日：1996-06-04
申请号：US533410
申请日：1995-09-25
申请人： Takashi Harada , Kazuhiro Yoshihara , Kazutaka Masuzawa , Kiyoshi Hayashi , Jun Kumazawa , Kenji Nagai , Masahiko Nishiuma , Chiyoshi Kamada
发明人： Takashi Harada , Kazuhiro Yoshihara , Kazutaka Masuzawa , Kiyoshi Hayashi , Jun Kumazawa , Kenji Nagai , Masahiko Nishiuma , Chiyoshi Kamada
IPC分类号： H01L23/12 , H01L23/13 , H01L23/498 , H01L23/66 , H01L39/02
CPC分类号： H01L23/13 , H01L23/49822 , H01L23/66 , H01L2224/16 , H01L2224/16235 , H01L2224/73253 , H01L2924/01079 , H01L2924/1305 , H01L2924/15153 , H01L2924/1517 , H01L2924/15173 , H01L2924/16195 , H01L2924/3011
摘要： For taking a characteristic impedance matching of signal transmission lines in a package which carries thereon a semiconductor chip with a very high-speed LSI formed thereon, there is provided a semiconductor integrated circuit device wherein one ends of signal transmission lines formed on a main surface of a package substrate are extended up to the position just under pads formed on a main surface of the semiconductor chip and are connected to the pads on the chip electrically through bump electrodes, while opposite ends of the signal transmission lines are extended to the outer peripheral portion of the main surface of the package substrate and outer leads are bonded thereto.
摘要翻译：为了在其上承载有非常高速LSI的半导体芯片的封装中采用信号传输线的特征阻抗匹配，提供了一种半导体集成电路器件，其中形成在主表面上的信号传输线的一端封装基板延伸到刚好在形成在半导体芯片的主表面上的焊盘下方的位置，并且通过凸块电极与芯片上的焊盘电连接，同时信号传输线的相对端延伸到外周部分的封装基板和外部引线的主表面接合。

10. 发明授权

US5267476A Strain detector 失效
标题翻译：应变检测器
公开(公告)号：US5267476A
公开(公告)日：1993-12-07
申请号：US757416
申请日：1991-09-10
申请人： Kiyoshi Hayashi , Hiromasa Ozawa
发明人： Kiyoshi Hayashi , Hiromasa Ozawa
IPC分类号： C25D3/56 , G01L1/12 , G01L3/10 , G01L3/00
CPC分类号： G01L3/102 , G01L1/125 , G01L3/103
摘要： A strain detector includes a passive member for receiving an external force, magnetostrictive layers formed on a surface of passive member and made of a magnetic material containing nickel and at least one kind of metal sulfide produced from reaction of a metal more reactive with sulfur than nickel with sulfur as an impurity, and a detection coil provided close to an exterior of magnetostrictive layers and used for detecting variations of permeability caused by strain of the magnetostrictive layers in response to the external force.
摘要翻译：应变检测器包括用于接收外力的被动元件，形成在被动元件表面上并由含有镍的磁性材料制成的磁致伸缩层，以及由比镍更能反应的金属与镍反应产生的至少一种金属硫化物以硫为杂质，以及检测线圈，靠近磁致伸缩层的外部设置，用于检测响应于外力的磁致伸缩层的应变引起的磁导率的变化。

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