专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070204681A1 Carbon thin line probe 有权
标题翻译：碳细线探头
公开(公告)号：US20070204681A1
公开(公告)日：2007-09-06
申请号：US11710974
申请日：2007-02-27
申请人： Masashi Kitazawa , Masaki Tanemura , Junya Tanaka , Tatsuhiko Okita
发明人： Masashi Kitazawa , Masaki Tanemura , Junya Tanaka , Tatsuhiko Okita
IPC分类号： G12B21/02 , B82B1/00 , B81B7/00
CPC分类号： G01Q70/12 , C12N15/89 , G01Q60/54 , Y10S977/86 , Y10S977/863 , Y10S977/875 , Y10S977/876 , Y10S977/879
摘要： A carbon thin line probe having a carbon thin line selectively formed at a projection-like terminal end portion thereof by means of an irradiation of high-energy beam, the carbon thin line internally containing a metal. Thereby achieved is a carbon thin line probe suitable for example for the probe of SPM cantilever, which has a high aspect ratio and high durability and reliability, capability of batch processing based on a simple manufacturing method, and to which magnetic characteristic can be imparted.
摘要翻译：一种碳细线探针，其具有通过高能束的照射在其突起状端部选择性地形成的碳细线，所述碳细线在内部含有金属。由此实现了适用于例如SPM悬臂的探针的碳细线探针，其具有高纵横比和高耐久性和可靠性，基于简单制造方法的批处理能力，并且可赋予其磁特性。

2. 发明授权

US08754471B2 Semiconductor device having gate in recess 有权
标题翻译：半导体器件具有凹槽中的栅极
公开(公告)号：US08754471B2
公开(公告)日：2014-06-17
申请号：US13040610
申请日：2011-03-04
申请人： Toshiaki Iwamatsu , Kozo Ishikawa , Masashi Kitazawa , Kiyoshi Hayashi , Takahiro Maruyama , Masaaki Shinohara , Kenji Kawai
发明人： Toshiaki Iwamatsu , Kozo Ishikawa , Masashi Kitazawa , Kiyoshi Hayashi , Takahiro Maruyama , Masaaki Shinohara , Kenji Kawai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66621 , H01L21/28 , H01L29/66795 , H01L29/772 , H01L29/7834 , Y02E10/50
摘要： There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.
摘要翻译：提供了可以在不劣化特性的情况下小型化的半导体器件及其制造方法。半导体器件包括：主表面，源极区域和漏极区域在主表面彼此分离形成的半导体衬底;形成在源区域和漏极区域之间的主表面上的栅电极层;第一形成为与源极区域的表面接触的导电层，以及形成为与漏极区域的表面接触的第二导电层。在主表面上形成凹部，以便通过栅极电极层下面的部分从第一导电层和源极区域之间的接触区域延伸到第二导电层和漏极区域之间的接触区域。

3. 发明授权

US08043918B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US08043918B2
公开(公告)日：2011-10-25
申请号：US12840430
申请日：2010-07-21
申请人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
发明人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
IPC分类号： H01L21/336
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer.
摘要翻译：为了以高生产率制造能够通过沟槽型元件隔离可靠地实现元件隔离并且能够有效地防止相邻元件的电位影响其他节点的半导体器件，制造半导体器件的方法包括：形成第一层; 通过蚀刻第一层和衬底形成沟槽的步骤; 热氧化沟槽内壁的步骤; 在包括沟槽的衬底上沉积膜厚度等于或大于沟槽的沟槽宽度的一半的第一导电膜的步骤; 通过CMP方法从第一层除去第一导电膜并保持第一导电膜仅留在沟槽中的步骤; 在沟槽内各向异性蚀刻第一导电膜的步骤，以调节导电膜的高度，使其低于衬底表面的高度; 通过CVD法在第一导电膜上沉积绝缘膜以将第一导电膜的上部嵌入沟槽内的步骤; 通过CMP方法使绝缘膜平坦化的步骤; 以及去除第一层的步骤。

4. 发明授权

US07791163B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07791163B2
公开(公告)日：2010-09-07
申请号：US11577878
申请日：2005-10-18
申请人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
发明人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
IPC分类号： H01L29/768
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.
摘要翻译：在制造半导体器件的过程中，在衬底上形成第一层，并且蚀刻第一层和衬底以形成沟槽。沟槽的内壁被热氧化。在包括沟槽内部的衬底上沉积厚度等于或大于沟槽宽度的一半的第一导电膜。通过化学机械抛光去除第一层上的第一导电膜，使得第一导电膜仅保留在沟槽中。通过各向异性蚀刻第一导电膜，将沟槽中的第一导电膜的高度调节为低于衬底的表面。通过化学气相沉积在衬底上沉积绝缘膜以覆盖沟槽中的第一导电膜的上表面。绝缘膜通过化学机械抛光而变平，第一层被去除。

5. 发明申请

US20080000293A1 Spm Cantilever and Manufacturing Method Thereof 有权
标题翻译： Spm悬臂及其制造方法
公开(公告)号：US20080000293A1
公开(公告)日：2008-01-03
申请号：US11587207
申请日：2005-04-20
申请人： Masashi Kitazawa , Ryo Ota , Masaki Tanemura
发明人： Masashi Kitazawa , Ryo Ota , Masaki Tanemura
IPC分类号： G01B5/28 , H01L21/00
CPC分类号： G01Q70/12 , Y10S977/849 , Y10S977/86
摘要： An SPM cantilever of the present invention including: a support portion (1) fabricated by processing a single crystal silicon wafer; a lever portion (2) formed in a manner extended from the support portion; a probe (3) disposed at a free end side of the lever portion; a coating of graphite film (5) covering all over the side on which the probe is formed and the entire probe; and a piece of thin line (6) consisting of a carbon nanofiber (CNF) or carbon nanotube (CNT) or graphite nanofiber (GNF) grown/formed from the graphite film at a probe terminal end portion (3a).
摘要翻译：本发明的SPM悬臂包括：通过处理单晶硅晶片制造的支撑部分（1）; 以从所述支撑部延伸的方式形成的杆部（2）设置在所述杆部的自由端侧的探针（3）覆盖在其上形成探针的一侧的整个探针的石墨膜（5）涂层; 以及由在探针终端部（3a）上由石墨膜生长/形成的碳纳米纤维（CNF）或碳纳米管（CNT）或石墨纳米纤维（GNF）组成的细线（6）。

6. 发明授权

US06694805B2 Cantilever for scanning probe microscopy 有权
标题翻译：悬臂扫描探针显微镜
公开(公告)号：US06694805B2
公开(公告)日：2004-02-24
申请号：US10122205
申请日：2002-04-16
申请人： Koichi Shiotani , Masashi Kitazawa , Kenji Sato , Akitoshi Toda
发明人： Koichi Shiotani , Masashi Kitazawa , Kenji Sato , Akitoshi Toda
IPC分类号： G01B528
CPC分类号： G01Q70/16 , G01Q70/10
摘要： A cantilever for Scanning Probe Microscopy including: a support portion; a lever portion extended from the support portion; and a probe portion provided at an free end of the lever portion, said probe portion being configured by two triangular thin plates each having one side respectively being one of the different two sides of a V-like notch formed on the free end of the lever, where the thin plates are caused to face each other while having the other side in common. The cantilever for Scanning Probe Microscopy is thereby achieved as having a probe portion which is light in weight and high in rigidity and is readily positioned in alignment and by which measurement at high resolution is steadily possible
摘要翻译：扫描探针显微镜的悬臂包括：支撑部分; 从所述支撑部延伸的杆部; 以及探针部，设置在所述杆部的自由端，所述探针部由两个三角形薄板构成，所述两个三角形薄板分别具有形成在所述杆的自由端上的V形切口的不同两侧之一，其中使薄板彼此面对，同时使另一侧相同。因此，扫描探针显微镜的悬臂具有重量轻且刚性高的探针部分，并且容易定位成对准，并且可以稳定地以高分辨率进行测量

7. 发明授权

US06664602B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US06664602B2
公开(公告)日：2003-12-16
申请号：US10194233
申请日：2002-07-15
申请人： Tomohiro Yamashita , Masashi Kitazawa
发明人： Tomohiro Yamashita , Masashi Kitazawa
IPC分类号： H01L29772
CPC分类号： H01L21/823892 , H01L21/76237 , H01L21/823878
摘要： An object of the invention is to suppress degradation of the effective isolation width between a well and a diffusion layer caused by impurity ion implantation for forming the well performed at a predetermined incident angle. A well is formed by performing impurity ion implantation twice: first impurity ion implantation from a first direction at predetermined incident angle, acceleration voltage and dose; and second impurity ion implantation from a second direction different from the first direction by 180 degrees in a plan view at the same incident angle, acceleration voltage and dose as those in the first impurity ion implantation.

8. 发明授权

US06521963B1 Semiconductor device and method of manufacturing semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06521963B1
公开(公告)日：2003-02-18
申请号：US09475199
申请日：1999-12-30
申请人： Kazunobu Ota , Masashi Kitazawa , Masayoshi Shirahata
发明人： Kazunobu Ota , Masashi Kitazawa , Masayoshi Shirahata
IPC分类号： H01L2976
CPC分类号： H01L29/6656 , H01L21/28061 , H01L21/28247 , H01L29/4983
摘要： A gate electrode (GE1) includes a polysilicon layer (4C), silicon oxide films (reoxidation films) 14, a metal layer (50C), and silicide films (15). The polysilicon layer (4C) is formed on a main surface (3BS) of a gate insulating film (3B), and the silicon oxide films (14) are formed on the side walls (4CW) of the polysilicon layer (4C). The metal layer (50C) is formed in contact with the main surface (4CS1) of the polysilicon layer (4C) on the opposite side to the gate insulating film (3B). The silicide films (15) are formed on the side walls (50CW) of the metal layer (50C) (which are composed of side walls (51CW and 52CW) of first and second metal layers (51 and 52)). After the silicide films (15) are formed, the metal layer (50C) is protected by the silicide films (15). This structure provides an MOS transistor having a polymetal gate in which oxidation of the metal layer is prevented to realize lower resistivity.
摘要翻译：栅电极（GE1）包括多晶硅层（4C），氧化硅膜（再氧化膜）14，金属层（50C）和硅化物膜（15）。多晶硅层（4C）形成在栅极绝缘膜（3B）的主表面（3BS）上，氧化硅膜（14）形成在多晶硅层（4C）的侧壁（4CW）上。金属层（50C）形成为与栅极绝缘膜（3B）相反侧的多晶硅层（4C）的主表面（4CS1）接触。硅化物膜（15）形成在金属层（50C）（由第一和第二金属层（51和52）的侧壁（51CW和52CW）构成）的侧壁（50CW）上。在形成硅化物膜（15）之后，金属层（50C）被硅化物膜（15）保护。该结构提供了具有多金属栅极的MOS晶体管，其中防止了金属层的氧化以实现较低的电阻率。

9. 发明授权

US06521517B1 Method of fabricating a gate electrode using a second conductive layer as a mask in the formation of an insulating layer by oxidation of a first conductive layer 失效
标题翻译：在通过第一导电层的氧化形成绝缘层时，使用第二导电层作为掩模来制造栅电极的方法
公开(公告)号：US06521517B1
公开(公告)日：2003-02-18
申请号：US09620138
申请日：2000-07-20
申请人： Kazunobu Ota , Masashi Kitazawa , Masayoshi Shirahata
发明人： Kazunobu Ota , Masashi Kitazawa , Masayoshi Shirahata
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/28247 , H01L21/32105 , H01L29/42376
摘要： A method of manufacturing a semiconductor device. The method includes forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, forming a first conductive layer on the gate insulating film, selectively forming a second conductive layer on the first conductive layer, and selectively imparting an insulating property to the first conductive layer by using the second conductive layer as a mask, to obtain an insulating layer. The method also includes forming a pair of source/drain regions of a second conductivity type opposite to the first conductivity type, so as to sandwich therebetween the surface of the semiconductor substrate underlying the first conductive layer left when the first conductive layer was imparted the insulating property.
摘要翻译：一种制造半导体器件的方法。该方法包括在第一导电类型的半导体衬底的表面上形成栅极绝缘膜，在栅极绝缘膜上形成第一导电层，在第一导电层上选择性地形成第二导电层，并选择性地赋予绝缘性通过使用第二导电层作为掩模到第一导电层，以获得绝缘层。该方法还包括形成与第一导电类型相反的第二导电类型的一对源极/漏极区域，以便当第一导电层被赋予绝缘体时在其间夹在其间的第一导电层下面的半导体衬底的表面属性。

10. 发明授权

US06333222B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06333222B1
公开(公告)日：2001-12-25
申请号：US09399369
申请日：1999-09-20
申请人： Masashi Kitazawa , Masayoshi Shirahata , Kazunobu Ohta
发明人： Masashi Kitazawa , Masayoshi Shirahata , Kazunobu Ohta
IPC分类号： H01L218244
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： In the method of manufacturing the DRAM mixed logic memory, first, a pattern of one gate electrode is formed, and then a pattern of another gate electrode is formed. A step of oxidizing a polycrystalline silicon residue is performed thereafter. Therefore, the polycrystalline silicon residue is prevented from being left and prevention of electric short circuit is allowed.
摘要翻译：在制造DRAM混合逻辑存储器的方法中，首先形成一个栅电极的图形，然后形成另一个栅电极的图形。此后进行氧化多晶硅残渣的步骤。因此，防止多晶硅渣残留，并且防止电气短路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式