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1. 发明申请

US20060164265A1 High rate coding for media noise 有权
公开(公告)号：US20060164265A1
公开(公告)日：2006-07-27
申请号：US11359453
申请日：2006-04-06
申请人： William Bliss , Andrei Vityaev , Razmik Karabed
发明人： William Bliss , Andrei Vityaev , Razmik Karabed
IPC分类号： H03M7/00
CPC分类号： G11B20/1426 , G11B20/10009 , G11B20/1833 , G11B2020/1446 , H03M5/145 , H03M13/093
摘要： An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.

2. 发明授权

US06788223B2 High rate coding for media noise 有权
标题翻译：高速编码媒体噪声
公开(公告)号：US06788223B2
公开(公告)日：2004-09-07
申请号：US10253911
申请日：2002-09-25
申请人： William G. Bliss , Andrei Vityaev , Razmik Karabed
发明人： William G. Bliss , Andrei Vityaev , Razmik Karabed
IPC分类号： H03M700
CPC分类号： G11B20/1426 , G11B20/10009 , G11B20/1833 , G11B2020/1446 , H03M5/145 , H03M13/093
摘要： An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.
摘要翻译：一种装置具有转换电路，预编码器电路和选择电路。转换电路转换用户数据b1，b2，b3。。。 bk到编码序列c0，c1，c2。。。 cq。选择电路以编码序列c0，c1，c2选择c0。。。 cq，使得预编码器电路的输出具有小于转换的最大数量q。转换电路可以包括用于转换用户数据b1，b2，b3的编码器电路。。。 bk到序列c1，c2。。。 cq，以及将c0加到序列c1，c2的转移最小化电路。。。 cq。该装置可以具有向编码序列c0，c1，c2添加至少一个附加位（可以是奇偶校验位）的电路。。。 cq。

3. 发明授权

US07178084B2 Short error propagation modulation coding method and device 有权
标题翻译：短误差传播调制编码方法及装置
公开(公告)号：US07178084B2
公开(公告)日：2007-02-13
申请号：US10253916
申请日：2002-09-25
申请人： William G. Bliss , Andrei Vityaev , Razmik Karabed
发明人： William G. Bliss , Andrei Vityaev , Razmik Karabed
IPC分类号： H03M13/00
CPC分类号： G11B20/1426 , H03M13/31
摘要： A data coding method produces codewords with a scheme that changes for different codewords, and decodes codewords with a scheme that remains constant for all codewords. The coding method receives k user bits, codes the user bits to produce k+r output bits, corrupts any one of the output bits, and accurately reproduces at least k−r−1 user bits. Codewords coded using the appropriate initial conditions are output. For each codeword, the appropriate initial conditions are appended to the codeword coded therefrom.
摘要翻译：数据编码方法产生具有针对不同码字改变的方案的码字，并且用对所有码字保持恒定的方案对码字进行解码。编码方法接收k个用户比特，对用户比特进行编码以产生k + r个输出比特，破坏任何一个输出比特，并且至少准确地再生k-r-1个用户比特。输出使用适当的初始条件编码的代码字。对于每个码字，适当的初始条件被附加到从其编码的码字。

4. 发明授权

US06774825B2 Modulation coding based on an ECC interleave structure 失效
标题翻译：基于ECC交错结构的调制编码
公开(公告)号：US06774825B2
公开(公告)日：2004-08-10
申请号：US10253909
申请日：2002-09-25
申请人： William G. Bliss , Andrei Vityaev , Razmik Karabed , Ali Najafi , Jonathan Ashley
发明人： William G. Bliss , Andrei Vityaev , Razmik Karabed , Ali Najafi , Jonathan Ashley
IPC分类号： H03M700
CPC分类号： H03M13/27 , G11B20/1426 , G11B20/1833 , G11B20/1866 , H03M5/145
摘要： A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks sorted into interleaves. A second encoder encodes a subset of the input blocks to produce output blocks, where the first encoder permutates a remainder of the input blocks and the output blocks to produce a codeword.
摘要翻译：基于ECC交错结构来调制编码的系统和方法包括编码包括被排序成交织的输入块的位的输入流的第一编码器。第二编码器编码输入块的子集以产生输出块，其中第一编码器排列剩余的输入块和输出块以产生码字。

5. 发明授权

US07274312B2 High rate coding for media noise 有权
标题翻译：高速编码媒体噪声
公开(公告)号：US07274312B2
公开(公告)日：2007-09-25
申请号：US11359453
申请日：2006-04-06
申请人： William G. Bliss , Andrei Vityaev , Razmik Karabed
发明人： William G. Bliss , Andrei Vityaev , Razmik Karabed
IPC分类号： H03M7/00
CPC分类号： G11B20/1426 , G11B20/10009 , G11B20/1833 , G11B2020/1446 , H03M5/145 , H03M13/093
摘要： An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b. . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.
摘要翻译：一种装置具有转换电路，预编码器电路和选择电路。转换电路转换用户数据b 1，b 2，b。。。对于编码序列c 0，c 1，c 2，...，。。 c 。选择电路在编码序列c 0 0，c 1，c 2 2中选择c <0> 0 。。。使得预编码器电路的输出具有小于转换的最大数量q。转换电路可以包括用于转换用户数据b 1，b 2，b 3 3的编码器电路。。。 c 到序列c 1，c 2。。。以及向序列c 1，c 2 2加上c 0的转换最小化电路。。。 c 。该装置可以具有电路，用于将至少一个额外的位（其可以是奇偶校验位）添加到编码序列c 0，c 1，c 2 。。。 c 。

6. 发明授权

US07053801B2 High rate coding for media noise 有权
标题翻译：高速编码媒体噪声
公开(公告)号：US07053801B2
公开(公告)日：2006-05-30
申请号：US10869843
申请日：2004-06-18
申请人： William G. Bliss , Andrei Vityaev , Razmik Karabed
发明人： William G. Bliss , Andrei Vityaev , Razmik Karabed
IPC分类号： H03M7/00
CPC分类号： G11B20/1426 , G11B20/10009 , G11B20/1833 , G11B2020/1446 , H03M5/145 , H03M13/093
摘要： An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.
摘要翻译：一种装置具有转换电路，预编码器电路和选择电路。转换电路转换用户数据b 1，b 2，b 3 3。。。对于编码序列c 0，c 1，c 2，...，。。 c 。选择电路在编码序列c 0 0，c 1，c 2 2中选择c <0> 0 。。。使得预编码器电路的输出具有小于转换的最大数量q。转换电路可以包括用于转换用户数据b 1，b 2，b 3 3的编码器电路。。。 c 到序列c 1，c 2。。。以及向序列c 1，c 2 2加上c 0的转换最小化电路。。。 c 。该装置可以具有电路，用于将至少一个额外的位（其可以是奇偶校验位）添加到编码序列c 0，c 1，c 2 。。。 c 。

7. 发明授权

US08892966B2 Methods and apparatus for soft data generation for memory devices using decoder performance feedback 有权
标题翻译：用于使用解码器性能反馈的存储器件的软数据生成的方法和装置
公开(公告)号：US08892966B2
公开(公告)日：2014-11-18
申请号：US13063899
申请日：2009-09-30
申请人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Clifton Williamson , Johnson Yen
发明人： Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Nenad Miladinovic , Andrei Vityaev , Clifton Williamson , Johnson Yen
IPC分类号： G06F11/00 , G11C29/00 , G11C7/04 , G11C16/04 , G11C16/26 , G11C7/02 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/1032 , G06F2212/2022 , G11C7/02 , G11C7/04 , G11C11/16 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5634
摘要： Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.
摘要翻译：用于使用解码器性能反馈的存储器件的软数据生成的方法和装置。通过从解码器获得性能反馈，在存储器件中产生至少一个软数据值; 基于性能反馈获得误差统计; 以及基于所获得的误差统计量生成所述至少一个软数据值。性能反馈包括解码比特中的一个或多个，基于由解码器解码的数据的多个错误比特和多个不满足的奇偶校验。

8. 发明授权

US08429500B2 Methods and apparatus for computing a probability value of a received value in communication or storage systems 有权
标题翻译：用于计算通信或存储系统中的接收值的概率值的方法和装置
公开(公告)号：US08429500B2
公开(公告)日：2013-04-23
申请号：US12751960
申请日：2010-03-31
申请人： Erich F. Haratsch , Nenad Miladinovic , Andrei Vityaev
发明人： Erich F. Haratsch , Nenad Miladinovic , Andrei Vityaev
IPC分类号： G11C29/00
CPC分类号： H03M13/612 , H03M13/1102 , H03M13/2957 , H03M13/3905 , H03M13/41 , H03M13/4138 , H04L1/005
摘要： Methods and apparatus are provided for computing a probability value of a received value in communication or storage systems. A probability value for a received value in a communication system or a memory device is computed by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the probability value using the set of parameters associated with the identified segment. A probability value for a received value in a communication system or a memory device can also be computed by calculating the probability value for the received value using a first distribution, wherein the first distribution is predefined and wherein a mapped version of the first distribution approximates a distribution of the received values and wherein the calculating step is implemented by a processor, a controller, a read channel, a signal processing unit or a decoder.
摘要翻译：提供了用于计算通信或存储系统中的接收值的概率值的方法和装置。通过获得至少一个接收值来计算通信系统或存储设备中的接收值的概率值; 识别对应于所接收的值的功能的片段，其中所述功能在多个片段上被定义，其中所述片段中的每个片段具有相关联的参数组; 以及使用与所识别的段相关联的参数集来计算概率值。也可以通过使用第一分布计算接收值的概率值来计算通信系统或存储器件中的接收值的概率值，其中第一分布是预定义的，并且其中第一分布的映射版本近似于分配接收值，其中计算步骤由处理器，控制器，读通道，信号处理单元或解码器来实现。

9. 发明申请

US20110216586A1 Methods And Apparatus For Intercell Interference Mitigation Using Modulation Coding 有权
标题翻译：使用调制编码的小区间干扰减轻的方法和装置
公开(公告)号：US20110216586A1
公开(公告)日：2011-09-08
申请号：US13001310
申请日：2009-06-30
申请人： Nils Graef , Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Andrei Vityaev , Johnson Yen
发明人： Nils Graef , Erich F. Haratsch , Milos Ivkovic , Victor Krachkovsky , Andrei Vityaev , Johnson Yen
IPC分类号： G11C16/12 , G11C16/04 , G11C16/26
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell.
摘要翻译：提供了使用调制编码的小区间干扰减轻的方法和装置。在闪速存储器的编程期间，执行调制编码，其选择用于编程闪速存储器的一个或多个级别，使得闪存中的减少数量的单元被编程为具有违反一个或多个预定标准的值。在读取闪速存储器期间，执行调制解码，其向闪存中的单元分配一个或多个电平，使得闪存中的单元数目减少，其值违反一个或多个预定准则。预定义的标准可以例如基于由编程的小区引起的干扰量的一个或多个; 编程单元的电压偏移：由编程单元存储的电压; 通过编程单元的电流变化量; 以及通过编程单元的电流量。

10. 发明授权

US07260167B1 Method and apparatus for synchronization of a bit stream for long latency date detection 有权
标题翻译：用于长时间延迟日期检测的位流同步的方法和装置
公开(公告)号：US07260167B1
公开(公告)日：2007-08-21
申请号：US10768907
申请日：2004-02-02
申请人： Pantas Sutardja , Andrei Vityaev
发明人： Pantas Sutardja , Andrei Vityaev
IPC分类号： H04L7/06
CPC分类号： H04L7/042 , G11B20/10009 , G11B20/1217 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1287 , G11B2020/1476
摘要： A method is for decoding a bit stream from a waveform representing the bit stream, having a first synchronization mark, data, and a second synchronization mark. Digitized samples are decoded to form a reconstructed bit stream. The reconstructed bit stream is then stored. At least one of the first synchronization mark and the second synchronization mark are then extracted from the reconstructed bit stream. Finally, the data are extracted from the reconstructed bit stream using an iterative decoding process, in accordance with at least one of the first synchronization mark and the second synchronization mark. As such, loss of the data between the first synchronization mark and the second synchronization mark, if there is a problem with the first synchronization mark, is avoided.
摘要翻译：一种方法是从表示具有第一同步标记，数据和第二同步标记的比特流的波形对比特流进行解码。数字样本被解码以形成重构比特流。然后存储重建的比特流。然后从重建的比特流中提取第一同步标记和第二同步标记中的至少一个。最后，根据第一同步标记和第二同步标记中的至少一个，使用迭代解码处理从重建的位流中提取数据。因此，避免了第一同步标记与第二同步标记之间的数据的丢失，如果存在第一同步标记的问题。

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