专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08875005B2 Systems and methods for low latency media defect detection 有权
公开(公告)号：US08875005B2
公开(公告)日：2014-10-28
申请号：US13368599
申请日：2012-02-08
申请人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
发明人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
IPC分类号： G06F11/00
摘要： Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

2. 发明授权

US08949701B2 Systems and methods for low latency media defect detection 有权
标题翻译：用于低延迟介质缺陷检测的系统和方法
公开(公告)号：US08949701B2
公开(公告)日：2015-02-03
申请号：US13368599
申请日：2012-02-08
申请人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
发明人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
IPC分类号： G06F11/00
CPC分类号： G11B20/10509 , G11B20/10046 , G11B20/10268 , G11B20/10472 , G11B20/1816 , G11B27/36 , G11B2220/2516 , H04L27/0002
摘要： Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.
摘要翻译：本发明的各种实施例提供了用于介质缺陷检测的系统和方法。例如，公开了一种媒体缺陷检测系统，其包括从介质导出的数据输入，快速包络计算电路，其接收数据输入并且基于数据输入提供快速衰减包络值;慢包络计算电路，其接收数据输入并基于数据输入提供慢衰减包络值，以及介质缺陷检测电路。媒体缺陷检测电路接收慢衰减包络值和快速衰减包络值，计算快速衰减包络值与慢衰减包络值的比值，并至少部分地基于比较来确定缺陷输出比值到缺陷阈值。

3. 发明申请

US20100074078A1 Systems and Methods for Low Latency Media Defect Detection 有权
标题翻译：低延迟介质缺陷检测系统与方法
公开(公告)号：US20100074078A1
公开(公告)日：2010-03-25
申请号：US12236148
申请日：2008-09-23
申请人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
发明人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
IPC分类号： G11B5/58
CPC分类号： G11B5/5565 , G11B5/59611 , G11B20/10037 , G11B20/1816 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.
摘要翻译：本发明的各种实施例提供了用于介质缺陷检测的系统和方法。例如，公开了一种媒体缺陷检测系统，其包括从介质导出的数据输入，快速包络计算电路，其接收数据输入并且基于数据输入提供快速衰减包络值;慢包络计算电路，其接收数据输入并基于数据输入提供慢衰减包络值，以及介质缺陷检测电路。媒体缺陷检测电路接收慢衰减包络值和快速衰减包络值，计算快速衰减包络值与慢衰减包络值的比值，并至少部分地基于比较来确定缺陷输出比值到缺陷阈值。

4. 发明申请

US20130205185A1 Systems and Methods for Low Latency Media Defect Detection 有权
标题翻译：低延迟介质缺陷检测系统与方法
公开(公告)号：US20130205185A1
公开(公告)日：2013-08-08
申请号：US13368599
申请日：2012-02-08
申请人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
发明人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
IPC分类号： G06F11/07
CPC分类号： G11B20/10509 , G11B20/10046 , G11B20/10268 , G11B20/10472 , G11B20/1816 , G11B27/36 , G11B2220/2516 , H04L27/0002
摘要： Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.
摘要翻译：本发明的各种实施例提供了用于介质缺陷检测的系统和方法。例如，公开了一种媒体缺陷检测系统，其包括从介质导出的数据输入，快速包络计算电路，其接收数据输入并且基于数据输入提供快速衰减包络值;慢包络计算电路，其接收数据输入并基于数据输入提供慢衰减包络值，以及介质缺陷检测电路。媒体缺陷检测电路接收慢衰减包络值和快速衰减包络值，计算快速衰减包络值与慢衰减包络值的比值，并至少部分地基于比较来确定缺陷输出比值到缺陷阈值。

5. 发明授权

US08139457B2 Systems and methods for low latency media defect detection 有权
标题翻译：用于低延迟介质缺陷检测的系统和方法
公开(公告)号：US08139457B2
公开(公告)日：2012-03-20
申请号：US12236148
申请日：2008-09-23
申请人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
发明人： Yang Cao , Scott M. Dziak , Nayak Ratnakar Aravind , Richard Rauschmayer , Weijun Tan
IPC分类号： G11B20/18
CPC分类号： G11B5/5565 , G11B5/59611 , G11B20/10037 , G11B20/1816 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.
摘要翻译：本发明的各种实施例提供了用于介质缺陷检测的系统和方法。例如，公开了一种媒体缺陷检测系统，其包括从介质导出的数据输入，快速包络计算电路，其接收数据输入并且基于数据输入提供快速衰减包络值;慢包络计算电路，其接收数据输入并基于数据输入提供慢衰减包络值，以及介质缺陷检测电路。媒体缺陷检测电路接收慢衰减包络值和快速衰减包络值，计算快速衰减包络值与慢衰减包络值的比值，并至少部分地基于比较来确定缺陷输出比值到缺陷阈值。

6. 发明申请

US20100208574A1 Systems and Methods for Reduced Latency Loop Recovery 有权
标题翻译：减少延迟循环恢复的系统和方法
公开(公告)号：US20100208574A1
公开(公告)日：2010-08-19
申请号：US12371906
申请日：2009-02-16
申请人： Nayak Ratnakar Aravind , Richard Rauschmayer
发明人： Nayak Ratnakar Aravind , Richard Rauschmayer
IPC分类号： G11B3/00 , H03G3/10
CPC分类号： H03G3/30 , G11B20/10009 , G11B20/10027 , G11B20/10481 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for reduced latency feedback in a data processing system. For example, some embodiments provide a data processing system that includes a variable gain amplifier, a processing circuit, a data detector, and an error signal calculation circuit. The variable gain amplifier amplifies a data input signal and provides an amplified signal. The processing circuit generates a signal output corresponding to the amplified signal, and includes a conditional multiplication circuit. The conditional multiplication circuit conditionally multiplies the signal output by a gain correction signal and provides the result as an interim output. The data detector applies a data detection algorithm to the signal output and provides an ideal output. The error signal calculation circuit generates a gain correction signal based at least in part on the interim output and a derivative of the ideal output. The level of amplification by the variable gain amplifier is based at least in part on the gain correction signal.
摘要翻译：本发明的各种实施例提供了用于在数据处理系统中减少等待时间反馈的系统和方法。例如，一些实施例提供了包括可变增益放大器，处理电路，数据检测器和误差信号计算电路的数据处理系统。可变增益放大器放大数据输入信号并提供放大信号。处理电路产生对应于放大信号的信号输出，并且包括条件乘法电路。条件乘法电路有条件地将输出的信号乘以增益校正信号，并将结果提供为临时输出。数据检测器将数据检测算法应用于信号输出，并提供理想的输出。误差信号计算电路至少部分地基于中间输出和理想输出的导数来产生增益校正信号。可变增益放大器的放大电平至少部分地基于增益校正信号。

7. 发明授权

US07957251B2 Systems and methods for reduced latency loop recovery 有权
标题翻译：降低延迟环路恢复的系统和方法
公开(公告)号：US07957251B2
公开(公告)日：2011-06-07
申请号：US12371906
申请日：2009-02-16
申请人： Nayak Ratnakar Aravind , Richard Rauschmayer
发明人： Nayak Ratnakar Aravind , Richard Rauschmayer
IPC分类号： G11B7/00
CPC分类号： H03G3/30 , G11B20/10009 , G11B20/10027 , G11B20/10481 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for reduced latency feedback in a data processing system. For example, some embodiments provide a data processing system that includes a variable gain amplifier, a processing circuit, a data detector, and an error signal calculation circuit. The variable gain amplifier amplifies a data input signal and provides an amplified signal. The processing circuit generates a signal output corresponding to the amplified signal, and includes a conditional multiplication circuit. The conditional multiplication circuit conditionally multiplies the signal output by a gain correction signal and provides the result as an interim output. The data detector applies a data detection algorithm to the signal output and provides an ideal output. The error signal calculation circuit generates a gain correction signal based at least in part on the interim output and a derivative of the ideal output. The level of amplification by the variable gain amplifier is based at least in part on the gain correction signal.
摘要翻译：本发明的各种实施例提供了用于在数据处理系统中减少等待时间反馈的系统和方法。例如，一些实施例提供了包括可变增益放大器，处理电路，数据检测器和误差信号计算电路的数据处理系统。可变增益放大器放大数据输入信号并提供放大信号。处理电路产生对应于放大信号的信号输出，并且包括条件乘法电路。条件乘法电路有条件地将输出的信号乘以增益校正信号，并将结果提供为临时输出。数据检测器将数据检测算法应用于信号输出，并提供理想的输出。误差信号计算电路至少部分地基于中间输出和理想输出的导数来产生增益校正信号。可变增益放大器的放大电平至少部分地基于增益校正信号。

8. 发明授权

US08176400B2 Systems and methods for enhanced flaw scan in a data processing device 有权
标题翻译：用于在数据处理设备中增强缺陷扫描的系统和方法
公开(公告)号：US08176400B2
公开(公告)日：2012-05-08
申请号：US12556180
申请日：2009-09-09
申请人： Weijun Tan , Shaohua Yang , Hongwei Song , Richard Rauschmayer
发明人： Weijun Tan , Shaohua Yang , Hongwei Song , Richard Rauschmayer
IPC分类号： H03M13/00
CPC分类号： H04L1/0057 , H04L1/0045
摘要： Various embodiments of the present invention provide systems and methods for flaw scan in a data processing system. As one example, a data processing system is disclosed that includes a data detector circuit, a bit sign inverting circuit, and an LDPC decoder circuit. The data detector circuit receives a verification data set that is an invalid LDPC codeword, and applies a data detection algorithm to the verification data set to yield a detected output. The bit sign inverting circuit modifies the sign of one or more elements of a first derivative of the detected output to yield a second derivative of the detected output. The second derivative of the detected output is an expected valid LDPC codeword. The LDPC decoder circuit applies a decoding algorithm to the second derivative of the detected output to yield a decoded output.
摘要翻译：本发明的各种实施例提供了在数据处理系统中的缺陷扫描的系统和方法。作为一个示例，公开了包括数据检测器电路，位符号反相电路和LDPC解码器电路的数据处理系统。数据检测器电路接收作为无效LDPC码字的验证数据集，并将数据检测算法应用于验证数据集以产生检测到的输出。位符号反相电路修改检测输出的一阶导数的一个或多个元素的符号，以产生检测到的输出的二阶导数。所检测的输出的二阶导数是期望的有效LDPC码字。 LDPC解码器电路将解码算法应用于检测输出的二阶导数，以产生解码输出。

9. 发明申请

US20100100788A1 Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel 有权
标题翻译：用于读通道的可编程准循环低密度奇偶校验（QC LDPC）编码器
公开(公告)号：US20100100788A1
公开(公告)日：2010-04-22
申请号：US12288221
申请日：2008-10-17
申请人： Shaohua Yang , Changyou Xu , Richard Rauschmayer , Hao Zhong , Weijun Tan
发明人： Shaohua Yang , Changyou Xu , Richard Rauschmayer , Hao Zhong , Weijun Tan
IPC分类号： H03M13/27 , G06F11/10
CPC分类号： H03M13/05 , G06F11/1008 , H03M13/116 , H03M13/2792
摘要： The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.
摘要翻译：本发明是用于编码用户数据的可编程QC LDPC编码器。编码器可以被配置为用读通道实现。编码器可以包括多个桶形移位器电路。桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。桶形移位器电路还被配置为输出奇偶校验位。编码器还可以包括编码器交织器存储器。编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。编码器交织器可以被配置为交织奇偶校验位。此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

10. 发明申请

US20090273492A1 Systems and Methods for Queue Based Data Detection and Decoding 有权
标题翻译：基于队列数据检测和解码的系统和方法
公开(公告)号：US20090273492A1
公开(公告)日：2009-11-05
申请号：US12114462
申请日：2008-05-02
申请人： Shaohua Yang , Hao Zhong , Weijun Tan , Richard Rauschmayer , Yuan Xing Lee
发明人： Shaohua Yang , Hao Zhong , Weijun Tan , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： H03M7/00
CPC分类号： H03M13/2987 , G11B20/18 , G11B2020/185 , G11B2220/2516 , H03M13/09 , H03M13/1102 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/3905 , H03M13/4146 , H03M13/6331 , H03M13/6337 , H04L1/005 , H04L1/0057 , H04L1/0065
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes at least a first detector, a second detector, a decoder, and a queuing buffer. The first detector is operable to perform a data detection on an input data set at a first time. The decoder receives a derivation of an output from the first detector and performs a decoding process. Where the decoding process fails to converge, the decoder output is passed to the second detector for a subsequent detection and decoding process at a second time.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括至少第一检测器，第二检测器，解码器和排队缓冲器的可变迭代数据处理系统。第一检测器可操作以在第一时间对输入数据集执行数据检测。解码器接收来自第一检测器的输出的导出并执行解码处理。在解码过程不能收敛的情况下，解码器输出被传送到第二检测器用于随后的检测和解码过程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式