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1. 发明授权

US08685284B2 Conducting paste for device level interconnects 有权
标题翻译：用于器件级互连的导电膏
公开(公告)号：US08685284B2
公开(公告)日：2014-04-01
申请号：US12884657
申请日：2010-09-17
申请人： Rabindra N. Das , Roy H. Magnuson , Mark D. Poliks , Voya R. Markovich
发明人： Rabindra N. Das , Roy H. Magnuson , Mark D. Poliks , Voya R. Markovich
IPC分类号： H01B1/00 , H01B1/22 , H01B1/02
CPC分类号： H01B1/22 , H01L2224/81 , Y10T29/49117
摘要： A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.
摘要翻译：导电糊和形成用于器件级互连的糊的方法。导电浆料含有80-95％范围内的金属负载，可用于制造五微米器件级互连。通过混合两种不同的导电浆料制成导电糊料，即使在最终固化后，每个糊料仍将其微量级独立富含区域保持在混合糊料中。一种糊状物含有至少一种低熔点合金，另一种糊状物含有贵金属填料如金或银薄片。通常，小于5微米的平均片尺寸适用于五微米互连。然而，对于5微米互连，优选1微米或更小的银薄片和LMP混合物。最终混合物中基于LMP的糊剂的量优选为20-50重量％。纳米微膏实施例显示良好的电收率（81％）和低接触电阻。

2. 发明授权

US08558374B2 Electronic package with thermal interposer and method of making same 失效
标题翻译：具有热插入件的电子封装及其制造方法
公开(公告)号：US08558374B2
公开(公告)日：2013-10-15
申请号：US13022654
申请日：2011-02-08
申请人： Voya R. Markovich , Rabindra N. Das , Frank D. Egitto , James J. McNamara, Jr.
发明人： Voya R. Markovich , Rabindra N. Das , Frank D. Egitto , James J. McNamara, Jr.
IPC分类号： H01L23/34 , H01L21/00
CPC分类号： H05K7/1061 , H01L23/473 , H01L23/49833 , H01L23/5389 , H01L2924/0002 , H05K1/0203 , H05K2201/10378 , H01L2924/00
摘要： An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package.
摘要翻译：具有夹在其间的插入件的两个电路化基板的电子封装件，所述插入器将基板电气互连，同时包括至少一个电气部件（例如，功率模块），其基本上在其中，以为所得到的封装提供甚至进一步的操作能力。

3. 发明授权

US08541687B2 Coreless layer buildup structure 有权
标题翻译：无芯层堆积结构
公开(公告)号：US08541687B2
公开(公告)日：2013-09-24
申请号：US12764993
申请日：2010-04-22
申请人： Voya Markovich , Timothy Antesberger , Frank D. Egitto , William Wilson , Rabindra N. Das
发明人： Voya Markovich , Timothy Antesberger , Frank D. Egitto , William Wilson , Rabindra N. Das
IPC分类号： H05K1/03 , H05K1/02 , H05K1/09
CPC分类号： H05K3/462 , H05K1/167 , H05K3/4069 , H05K3/4623 , H05K3/4632 , H05K2203/0191 , H05K2203/061 , H05K2203/063
摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.
摘要翻译：一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。

4. 发明授权

US08499445B1 Method of forming an electrically conductive printed line 有权
标题翻译：形成导电印刷线的方法
公开(公告)号：US08499445B1
公开(公告)日：2013-08-06
申请号：US13184699
申请日：2011-07-18
申请人： Rabindra N. Das , Frank D. Egitto , Voya R. Markovich
发明人： Rabindra N. Das , Frank D. Egitto , Voya R. Markovich
IPC分类号： H05K3/40
CPC分类号： H05K3/246 , H05K3/1216 , H05K3/125 , H05K3/243 , H05K2201/0245 , H05K2203/0425 , H05K2203/072 , H05K2203/095 , Y10T29/49155 , Y10T29/49156 , Y10T29/49162 , Y10T29/49165
摘要： Printed conductive lines and a method of preparing them using polymer nanocomposites with low resistivity and high current carrying capacity. Plasma treatment selectively removes polymers/organics from nanocomposites. Subsequent selective metal is deposited on top of the exposed metal surface of the printed conductive lines in order to improve current carrying capacity of the conductive printed lines. The printed conductive lines use a conductive ink or printing process and are then cured thermally and/or by a lamination process. Next, the printed conductive lines are treated with the plasma for 5-15 minutes in order to remove organics. E-less copper (Cu) is selectively deposited only at the conducting particle surface of the printed conductive lines. If desired, e-less gold, silver, tin, or tin-lead can be deposited on top of the e-less Cu.
摘要翻译：印刷导电线及其使用具有低电阻率和高载流能力的聚合物纳米复合材料制备它们的方法。等离子体处理选择性地从纳米复合材料中除去聚合物/有机物。随后的选择性金属沉积在印刷导线的暴露的金属表面的顶部上，以便改善导电印刷线的载流能力。印刷的导线使用导电油墨或印刷工艺，然后热固化和/或通过层压工艺固化。接下来，印刷的导线用等离子体处理5-15分钟以除去有机物。仅在印刷导线的导电粒子表面选择性地沉积无电铜（Cu）。如果需要，可以在无电镀铜的顶部上沉积无电镀金，银，锡或锡铅。

5. 发明授权

US08445094B2 Circuitized substrate with dielectric layer having dielectric composition not including continuous or semi-continuous fibers 有权
标题翻译：具有介电层的电路化基底，其电介质组成不包括连续或半连续的纤维
公开(公告)号：US08445094B2
公开(公告)日：2013-05-21
申请号：US11896786
申请日：2007-09-06
申请人： Robert Japp , Kostas Papathomas
发明人： Robert Japp , Kostas Papathomas
IPC分类号： B32B3/24 , H05K1/03
CPC分类号： H05K1/0373 , H01L2224/16225 , H01L2924/15311 , H05K3/4602 , H05K2201/0209 , H05K2201/0239 , Y10T428/24322 , Y10T428/24355 , Y10T428/24917
摘要： A circuitized substrate which includes at least one circuit layer and at least one substantially solid dielectric layer comprised of a dielectric composition which includes a cured resin material and a predetermined percentage by weight of particulate fillers, but not including continuous or semi-continuous fibers as part thereof.
摘要翻译：一种电路化衬底，其包括至少一个电路层和至少一个基本上固体的电介质层，该电介质层包括固化树脂材料和预定重量百分比的颗粒填料，但不包括连续或半连续纤维作为部分其中。

6. 发明申请

US20130033827A1 ELECTRICALLY CONDUCTIVE ADHESIVE (ECA) FOR MULTILAYER DEVICE INTERCONNECTS 有权
标题翻译：用于多层设备互连的电导体粘合剂（ECA）
公开(公告)号：US20130033827A1
公开(公告)日：2013-02-07
申请号：US13198756
申请日：2011-08-05
申请人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
发明人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
IPC分类号： H05K5/00 , H05K1/09 , B23K31/02 , H05K1/00 , H01B1/00 , H01B1/02
CPC分类号： H05K1/0313 , B23K26/382 , B23K26/40 , B23K2101/40 , B23K2103/16 , B23K2103/172 , B23K2103/52 , H01B1/22 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01322 , H01L2924/15311 , H05K1/097 , H05K3/4053 , H05K3/4069 , H05K3/462 , H05K3/4623 , H05K3/4641 , H05K2201/0257 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09718 , H05K2201/10378 , H05K2203/0425 , H05K2203/1152 , Y10T29/49128 , Y10T29/49165 , H01L2924/00
摘要： A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.
摘要翻译：用于连接多级Z轴互连的多层导电粘合剂（ECA）混合物和形成连接多级Z轴互连的ECA的方法。具有多层能力的ECA包含允许糊料适应特定要求的组成成分的混合物，其中制造电路化衬底组件的方法，其中具有潜在不同的热膨胀系数（CTE）的两个或更多个子组件对齐，并且Z- 在连接期间创建轴互连。导体的冶金和多层导电浆料的冶金被有效地混合，并且在配合子组件之间使用的可流动的中间电介质流动以接合和围绕导体耦合。

7. 发明申请

US20120260063A1 MODULAR, DETACHABLE COMPUTE LEAF FOR USE WITH COMPUTING SYSTEM 审中-公开
标题翻译：具有计算机系统的模块化，可分离的计算机叶片
公开(公告)号：US20120260063A1
公开(公告)日：2012-10-11
申请号：US13082599
申请日：2011-04-08
申请人： Voya R. Markovich , How T. Lin , Benson Chan , Frank D. Egitto
发明人： Voya R. Markovich , How T. Lin , Benson Chan , Frank D. Egitto
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： H05K3/365 , H01L2924/0002 , H05K1/148 , H05K2201/047 , H05K2201/10159 , H05K2201/209 , H01L2924/00
摘要： A detachable, logic leaf module having dendritic projections on a surface is connected to a recessed area on the surface of a cluster interface board. The projections are used for electrically connecting the logic module device to the cluster interface board or the like, the projections on the surface of the logic leaf being flexibly and conductively wired to the receiving area on the surface of the cluster interface board. The logic leaf connector is removable without the need for solder softening thermal cycles or special tools, and permits the simple removal or replacement of an individual leaf at any time.
摘要翻译：在表面上具有树状突起的可拆卸的逻辑叶片模块连接到集群接口板的表面上的凹陷区域。突起用于将逻辑模块设备电连接到集群接口板等，逻辑叶片的表面上的突起被灵活地和导电地连接到集群接口板的表面上的接收区域。逻辑叶片连接器是可移动的，不需要焊料软化热循环或特殊工具，并且允许在任何时间简单地移除或更换单个叶片。

8. 发明申请

US20120160544A1 CORELESS LAYER BUILDUP STRUCTURE WITH LGA 有权
标题翻译：无缝层建筑结构与LGA
公开(公告)号：US20120160544A1
公开(公告)日：2012-06-28
申请号：US12764994
申请日：2010-04-22
申请人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
发明人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
IPC分类号： H05K1/00 , H05K1/09 , H05K1/03
CPC分类号： H05K3/4623 , H05K1/092 , H05K3/4053 , H05K3/4614 , H05K3/4691 , H05K2203/061
摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.
摘要翻译：一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。衬底还可以包含焊盘阵列（LGA）封装。

9. 发明授权

US08196281B2 Method of applying force to electrical contacts on a printed circuit board 失效
标题翻译：对印刷电路板上的电触点施加力的方法
公开(公告)号：US08196281B2
公开(公告)日：2012-06-12
申请号：US13090676
申请日：2011-04-20
申请人： Benson Chan , Matthew J. Lauffer
发明人： Benson Chan , Matthew J. Lauffer
IPC分类号： H01S4/00
CPC分类号： H05K7/1061 , H05K7/1007 , Y10T29/49002 , Y10T29/49204 , Y10T29/49222 , Y10T29/53174 , Y10T29/53209 , Y10T29/53213 , Y10T29/53283 , Y10T29/53678
摘要： A spring actuated clamping mechanism has a backer plate with an upper surface and a lower surface. A set of apertures is formed along the periphery of the backer plate. The upper surface of the backer plate has at least one backer plate recess, and preferably four recesses, formed therein. A threaded aperture is also formed in the backer plate. A compression plate is also provided. A second set of apertures is formed along the periphery of the compression plate. The lower surface of the compression plate has at least one compression plate recess, and at least one compression plate aperture. At least one compression spring is disposed between the backer plate and the compression plate. A screw tension release mechanism is screwed into the backer plate threaded aperture and inserted through the compression plate aperture. When the release mechanism is loosened, backer plate is forced downwardly, applying a uniform force to all electrical contacts on the printed circuit board or card to which the clamping mechanism is attached.
摘要翻译：弹簧致动夹紧机构具有带有上表面和下表面的支承板。沿着支撑板的周边形成一组孔。背板的上表面具有至少一个支承板凹部，最好在其中形成四个凹部。螺纹孔也形成在后板中。还提供压缩板。沿着压缩板的周边形成第二组孔。压缩板的下表面具有至少一个压缩板凹部和至少一个压缩板孔。至少一个压缩弹簧设置在支承板和压缩板之间。螺钉张力释放机构拧入支承板螺纹孔并插入通过压板孔。当释放机构松动时，支撑板向下受力，对夹紧机构所附着的印刷电路板或卡上的所有电触头施加均匀的力。

10. 发明申请

US20120112345A1 HIGH BANDWIDTH SEMICONDUCTOR BALL GRID ARRAY PACKAGE 审中-公开
标题翻译：高带宽半导体球形阵列阵列
公开(公告)号：US20120112345A1
公开(公告)日：2012-05-10
申请号：US12939659
申请日：2010-11-04
申请人： Kim J. Blackwell , Frank D. Egitto , Voya R. Markovich
发明人： Kim J. Blackwell , Frank D. Egitto , Voya R. Markovich
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/4857 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： A high bandwidth semiconductor printed circuit board assembly (PCBA) providing a layer of dielectric substrate containing plated vias with an upper and lower surface plated with etched copper, mated with a second layer of etched copper plated dielectric containing plated vias that is placed on the top surface of the first layer. A third layer of etched copper plated dielectric containing plated vias may be placed on the bottom layer of etched copper foil. A base layer of etched copper plated thick dielectric containing plated vias is laminated simultaneously with the preceding layers to provide the high bandwidth digital and RF section of the assembly.
摘要翻译：一种高带宽半导体印刷电路板组件（PCBA），其提供包含电镀通孔的电介质基板层，其上表面和下表面镀有蚀刻铜，与第二层蚀刻镀铜电介质配合，该电镀层包含镀覆通孔第一层的表面。可以在蚀刻铜箔的底层上放置包含镀敷通孔的蚀刻镀铜电介质的第三层。蚀刻的镀铜厚电介质的基底层含有电镀通孔与先前的层同时层压，以提供组件的高带宽数字和RF部分。

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