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1. 发明授权

US08228096B2 Circuit and method for current-mode output driver with pre-emphasis 有权
标题翻译：电流模式输出驱动器的电路和方法，预加重
公开(公告)号：US08228096B2
公开(公告)日：2012-07-24
申请号：US11712914
申请日：2007-03-02
申请人： Yoshinori Nishi
发明人： Yoshinori Nishi
IPC分类号： H03K3/00 , H03K19/094 , H03K5/01
CPC分类号： H04L25/0286 , H04L25/0278
摘要： An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.
摘要翻译：一种输出驱动器电路，包括接收第一数据信号的预驱动器级，所述预驱动级包括基于所述第一数据信号执行电流减法以输出第二数据信号的多个第一差分对，以及输出驱动器所述输出驱动级包括沿着传输线传输输出信号的多个第二差分对，所述预驱动级与所述预驱动级接收所述第二数据信号。

2. 发明授权

US08194090B2 Method of controlling frame memory, memory control circuit, and image processing apparatus including the memory control circuit 有权
标题翻译：控制帧存储器的方法，存储器控制电路和包括存储器控制电路的图像处理装置
公开(公告)号：US08194090B2
公开(公告)日：2012-06-05
申请号：US12318994
申请日：2009-01-14
申请人： Shinsuke Sato
发明人： Shinsuke Sato
IPC分类号： G09G5/36 , G06F12/00 , G06F12/06
CPC分类号： G09G3/3611 , G09G5/393 , G09G5/395 , G09G2340/16 , G09G2360/128
摘要： Various exemplary embodiments provide methods of controlling frame memory, memory control circuits, and image processing apparatuses including the memory control circuits. Data representing values of pixels constituting each of a plurality of frames are received in an order of the frames, and data representing values of pixels constituting a previous frame are read from the frame memory and data representing values of pixels constituting a next frame are written to the frame memory. By reading first data representing values of a portion of the pixels constituting the previous frame from the frame memory before receiving of data representing values of pixels constituting the next frame starts, a delay time before starting to output data representing values of pixels of the previous frame can be shortened.
摘要翻译：各种示例性实施例提供了控制帧存储器，存储器控制电路和包括存储器控制电路的图像处理装置的方法。以帧的顺序接收表示构成多个帧的像素的值的数据，从帧存储器读出表示构成前一帧的像素的数据，表示构成下一帧的像素的值的数据被写入帧存储器。在接收到表示构成下一帧的像素的值的数据的开始之前，通过从帧存储器读取表示构成前一帧的一部分像素的值的第一数据开始，开始输出表示前一帧的像素值的数据的延迟时间可以缩短。

3. 发明授权

US08164597B2 Color conversion circuit and method of color conversion using interpolation from conversion coefficients some of which are substituted 有权
标题翻译：颜色转换电路和颜色转换方法使用插值从其中一些被替换的转换系数
公开(公告)号：US08164597B2
公开(公告)日：2012-04-24
申请号：US12078444
申请日：2008-03-31
申请人： Yoshinori Watanabe
发明人： Yoshinori Watanabe
IPC分类号： G09G5/02
CPC分类号： G09G5/02 , G09G2340/06
摘要： Exemplary embodiments of color conversion circuits and color conversion methods convert input color data into output color data. The input color data is positioned in a three-dimensional color space, which is divided into a plurality of unit cubes each having a fixed dimension. The input color data is converted by performing interpolations using conversion coefficients at vertexes of the unit cube within which the input color data is positioned. When the input color data is positioned on a gray axis of the color space, a substitution circuit substitutes some of the conversion coefficients such that the interpolation becomes a linear interpolation. As a result, it is assured that input color data positioned on the gray axis is converted to gray output color data.
摘要翻译：颜色转换电路和颜色转换方法的示例性实施例将输入颜色数据转换成输出颜色数据。输入颜色数据被定位在三维颜色空间中，其被分成多个单位立方体，每个单位立方体具有固定的尺寸。通过使用在输入颜色数据所在的单位立方体的顶点处的转换系数进行内插来转换输入颜色数据。当输入颜色数据位于颜色空间的灰色轴上时，替代电路将一些转换系数代替，使得插值成为线性内插。结果，确保位于灰色轴上的输入颜色数据被转换为灰色输出颜色数据。

4. 发明申请

US20110299397A1 COMMUNICATION CONTROL APPARATUS AND SHAPING APPARATUS HAVING TOKEN BUCKET 有权
标题翻译：通信控制装置和具有托架的形状装置
公开(公告)号：US20110299397A1
公开(公告)日：2011-12-08
申请号：US13151829
申请日：2011-06-02
申请人： Rui FUKUCHI
发明人： Rui FUKUCHI
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L47/527 , H04L47/6255 , H04L49/503
摘要： Various exemplary shaping apparatuses for shaping packets stored in queues are provided. The shaping apparatus includes a token bucket that accumulates tokens with a predetermined rate. When a number of tokens accumulated in the token bucket is equal to or larger than a reference number corresponding to a maximum packet length that the queues may store, the shaping apparatus allows one of the packets stored in the queues to transmit and subtracts a number of tokens corresponding to a length of the packet allowed to be transmitted. Various exemplary communication control apparatuses that incorporate the shaping apparatuses are also provided.
摘要翻译：提供了用于对存储在队列中的分组进行整形的各种示例性整形装置。整形装置包括以预定速率累加令牌的令牌桶。当令牌桶中积累的多个令牌等于或大于与队列可存储的最大分组长度对应的参考号时，整形装置允许存储在队列中的分组之一发送和减去一些对应于允许发送的分组的长度的令牌。还提供了并入成形设备的各种示例性通信控制设备。

5. 发明申请

US20110001531A1 Method and apparatus for receiving burst data without using external detection signal 有权
标题翻译：用于在不使用外部检测信号的情况下接收脉冲串数据的方法和装置
公开(公告)号：US20110001531A1
公开(公告)日：2011-01-06
申请号：US12801835
申请日：2010-06-28
申请人： Yoshinori Nishi , Masahiro Konishi
发明人： Yoshinori Nishi , Masahiro Konishi
IPC分类号： H03L7/00
CPC分类号： H04L7/0075 , H03L7/0807 , H03L7/104 , H03L7/143 , H04L7/0083 , H04L7/033 , H04L7/046 , H04L7/10
摘要： Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.
摘要翻译：公开了用于在不使用外部检测信号的情况下接收突发数据信号的装置和方法。该装置可以包括用于产生时钟信号的时钟数据恢复（CDR）电路，以及用于检测从输入信号恢复的数据中的初始部分的检测电路。 CDR电路可以具有尝试将时钟信号与参考数据信号同步的第一模式，以及尝试使时钟信号与突发数据信号同步并基于时钟信号恢复数据的第二模式。该装置可以包括控制器，以进行包括依次将CDR电路设置为第一模式的过程，将CDR电路设置为第二模式，并且当检测电路检测到初始部分时将CDR电路保持在第二模式在恢复的数据。

6. 发明申请

US20100271739A1 Semiconductor integrated circuit having protection circuit capable of protecting against ESD and EOS 有权
标题翻译：具有能够防止ESD和EOS的保护电路的半导体集成电路
公开(公告)号：US20100271739A1
公开(公告)日：2010-10-28
申请号：US12662522
申请日：2010-04-21
申请人： Hajime Hirata
发明人： Hajime Hirata
IPC分类号： H02H9/04
CPC分类号： H01L27/0266
摘要： A semiconductor integrated circuit has an internal circuit having an input terminal connected to a connection terminal, a protection circuit that discharges an over-voltage supplied to the connection terminal to a power line. The protection circuit includes a first discharge circuit connected to the connection terminal, a second discharge circuit connected to the connection terminal and discharges the over-voltage to the power line, and an over-voltage detect circuit that detects a discharge current flowing through the second discharge circuit and generates an over-voltage detect signal when the discharge current is detected. The first discharge circuit is disabled to discharge the over-voltage when the over-voltage detect signal is supplied.
摘要翻译：半导体集成电路具有内部电路，其具有连接到连接端子的输入端子，将提供给连接端子的过电压放电到电力线路的保护电路。保护电路包括连接到连接端子的第一放电电路，连接到连接端子的第二放电电路，并将过电压放电到电源线;以及过电压检测电路，检测流过第二放电电流的放电电流并且当检测到放电电流时产生过电压检测信号。当提供过电压检测信号时，第一放电电路被禁止放电过电压。

7. 发明授权

US07691277B2 Quartz component for plasma processing apparatus and restoring method thereof 有权
标题翻译：用于等离子体处理装置的石英组件及其恢复方法
公开(公告)号：US07691277B2
公开(公告)日：2010-04-06
申请号：US12071041
申请日：2008-02-14
申请人： Katsunori Suzuki , Kenji Nakamura
发明人： Katsunori Suzuki , Kenji Nakamura
IPC分类号： H01L21/302 , B24B1/00
CPC分类号： H01L21/67069 , H01J37/32623 , Y10S438/905
摘要： The main surface of a quartz component is divided by an offset into a first region having a larger height around an inner perimeter and a second region adjacent to the outer perimeter of the first region. Repeated restoration of a damaged component by forming a bulge on the first region and machining the bulge to make a flat surface while maintaining the offset enables long term use of the component.
摘要翻译：石英部件的主表面被偏移分隔成围绕内周边具有较大高度的第一区域和与第一区域的外周边相邻的第二区域。通过在第一区域上形成凸起并加工凸起以形成平坦的表面同时保持偏移来重复地恢复损坏部件，可以长期使用部件。

8. 发明授权

US07671881B2 Timing detection circuit and apparatus for modulating light beam 有权
标题翻译：定时检测电路和调制光束的装置
公开(公告)号：US07671881B2
公开(公告)日：2010-03-02
申请号：US11892490
申请日：2007-08-23
申请人： Ryoji Okazaki
发明人： Ryoji Okazaki
IPC分类号： B41J2/47 , B41J2/435
CPC分类号： H04N1/047 , H04N2201/02439 , H04N2201/0471 , H04N2201/04744 , H04N2201/04781 , H04N2201/04784 , H04N2201/04794
摘要： A timing detection circuit including a first timing detection circuit, a second detection circuit, and an output circuit is disclosed. The first detection circuit detects, among multiphase clocks having n mutually different phases and a frequency of k times the frequency of a reference clock, a closest clock having a clock edge closest to a valid edge of the synchronizing signal and generates first detect signal DET_A indicating the detected clock. The second timing detection circuit detects within which of k successive cycles of the representative clock selected from the multiphase clocks the valid edge of the synchronizing signal is positioned and generates second detect signal DET_B indicating the detected cycle. The output circuit receives the first detect signal and the second detect signal and outputs first output signal OUT_A and second output signal OUT_B.
摘要翻译：公开了一种包括第一定时检测电路，第二检测电路和输出电路的定时检测电路。第一检测电路在具有n个相互不同的相位的多相时钟和基准时钟的频率的k倍的多相时钟中检测最近的时钟，其具有最接近同步信号的有效边沿的时钟边缘，并且生成第一检测信号DET_A，检测到的时钟。第二定时检测电路检测从多相时钟选择的代表时钟的k个连续周期中的同步信号的有效边位于哪个中，并产生指示检测到的周期的第二检测信号DET_B。输出电路接收第一检测信号和第二检测信号，并输出第一输出信号OUT_A和第二输出信号OUT_B。

9. 发明授权

US07586380B1 Bias circuit to stabilize oscillation in ring oscillator, oscillator, and method to stabilize oscillation in ring oscillator 有权
标题翻译：用于稳定环形振荡器振荡的偏置电路，振荡器和稳定环形振荡器振荡的方法
公开(公告)号：US07586380B1
公开(公告)日：2009-09-08
申请号：US12073958
申请日：2008-03-12
申请人： Ananda S. Natarajan , Jithin Janardhan
发明人： Ananda S. Natarajan , Jithin Janardhan
IPC分类号： H03B5/24 , H03K3/03 , H03L1/00 , H03L1/02
CPC分类号： H03K5/133 , H03K3/011 , H03K3/0322 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143 , H03K2005/00202 , H03K2005/00208 , H03L1/00
摘要： Bias circuits to stabilize oscillation in ring oscillators, oscillators, and methods to stabilize oscillation in ring oscillators are provided. The ring oscillator includes a plurality of differential delay cells, each including a pair of input transistors, a pair of voltage-controlled resistors, and a common current source. The bias circuit includes a replica arm that includes a replica of one of the voltage-controlled resistors, and a resistor arm that includes a fixed resistor. The bias circuit supplies bias voltages to the differential delay cells such that ratio of voltage swing to bias current of the delay cell is kept constant by referring the ratio to the fixed resistor.
摘要翻译：提供了用于稳定环形振荡器中的振荡的偏置电路，振荡器和稳定环形振荡器中的振荡的方法。环形振荡器包括多个差分延迟单元，每个差分延迟单元包括一对输入晶体管，一对压控电阻器和公共电流源。偏置电路包括复制臂，其包括压控电阻器之一的副本，以及包括固定电阻器的电阻臂。偏置电路向差分延迟单元提供偏置电压，使得延迟单元的电压摆幅与偏置电流的比率通过参考固定电阻器的比率而保持恒定。

10. 发明申请

US20090103334A1 Switching-type power-supply unit and a method of switching in power-supply unit 有权
标题翻译：开关式电源单元和电源单元切换方式
公开(公告)号：US20090103334A1
公开(公告)日：2009-04-23
申请号：US12285826
申请日：2008-10-15
申请人： Ichiro Tamaki
发明人： Ichiro Tamaki
IPC分类号： H02M7/00
CPC分类号： H02M1/4258 , H02M3/33507 , Y02B70/126
摘要： A switching-type power-supply which enables the switching with little power loss and a method of switching the switching-type power-supply are provided. The switching-type power-supply unit includes a transformer with primary, secondary, winding and control windings, a switch which switches supply of a primary current from a dotted terminal to a non-dotted terminal through the primary winding, a rectifying diode connected the secondary winding, a monitoring signal generation circuit with a diode and a resistor, the diode between GND and a dotted terminal of the control winding, the resistor between GND and a non-dotted terminal of the control winding, the monitoring signal generation circuit generating a monitoring signal at the dotted terminal of the control winding, and a control unit with a zero-point detector and a controller. The zero-point detector monitoring the monitoring signal and supplying a detection signal to the controller. The controller determining on-timing of the switch based on the detection signal supplied from the zero-point detector.
摘要翻译：提供了能够进行小功率切换的开关型电源以及开关型电源的切换方法。开关型电源单元包括具有初级，次级，绕组和控制绕组的变压器，开关，其通过初级绕组将点电端子的初级电流提供给非点状端子;整流二极管，二次绕组，具有二极管和电阻的监测信号发生电路，GND与控制绕组的虚线端之间的二极管，GND与控制绕组的无点端之间的电阻，监测信号产生电路产生一个在控制绕组的虚线端子处的监视信号，以及具有零点检测器和控制器的控制单元。零点检测器监测监控信号并向控制器提供检测信号。控制器基于从零点检测器提供的检测信号来确定开关的接通定时。

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