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1. 发明授权

US09991378B2 Trench power semiconductor device 有权
公开(公告)号：US09991378B2
公开(公告)日：2018-06-05
申请号：US15186685
申请日：2016-06-20
申请人： SINOPOWER SEMICONDUCTOR, INC.
发明人： Po-Hsien Li , Wei-Chieh Lin , Jia-Fu Lin , Guo-Liang Yang
IPC分类号： H01L29/66 , H01L29/78 , H01L29/40 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer.

2. 发明授权

US08643094B2 Method of forming a self-aligned contact opening in MOSFET 有权
标题翻译：在MOSFET中形成自对准接触开口的方法
公开(公告)号：US08643094B2
公开(公告)日：2014-02-04
申请号：US13218476
申请日：2011-08-26
申请人： Sung-Shan Tai , Teng-hao Yeh , Chia-Hui Chen
发明人： Sung-Shan Tai , Teng-hao Yeh , Chia-Hui Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/41741 , H01L29/41766 , H01L29/41775 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.
摘要翻译：提出了在半导体衬底中形成接触开口的方法。在半导体衬底中形成各自具有突出部分的多个沟槽栅极，并且在突出部分上延伸的半导体衬底上沉积停止层，其中沿着突出部分的每个侧壁的阻挡层的每个部分是被间隔物覆盖。通过利用阻挡层对间隔物的相对较高的蚀刻选择性去除未被间隔物覆盖的停止层的部分，可以形成每个侧壁上具有L型形状的相邻突出部分之间的开口，并且可以形成光刻此后可以进行处理以形成自对准的接触开口。

3. 发明授权

US08178923B2 Power semiconductor device having low gate input resistance 有权
标题翻译：具有低栅极输入电阻的功率半导体器件
公开(公告)号：US08178923B2
公开(公告)日：2012-05-15
申请号：US12840283
申请日：2010-07-20
申请人： Wei-Chieh Lin , Guo-Liang Yang , Jia-Fu Lin , Shian-Hau Liao
发明人： Wei-Chieh Lin , Guo-Liang Yang , Jia-Fu Lin , Shian-Hau Liao
IPC分类号： H01L23/48
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/4925 , H01L29/66727 , H01L29/66734
摘要： A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.
摘要翻译：提供了具有低栅极输入电阻的功率半导体器件及其制造方法。功率半导体器件包括至少沟槽晶体管，导电层，金属接触插塞，绝缘层，层间电介质，栅极金属层和源极金属层的衬底。金属接触插头可以用作掩埋栅极金属总线，并且金属接触插塞可以在源极金属层下方通过，并保持源极金属层的面积完整。因此，本发明可以在不划分源极金属层的情况下提供较低的栅极输入电阻，因此源极金属层可以具有用于随后的封装和接合工艺的更大和完整的面积。

4. 发明授权

US08860134B1 Trench power device and manufacturing method thereof 有权
标题翻译：沟槽动力装置及其制造方法
公开(公告)号：US08860134B1
公开(公告)日：2014-10-14
申请号：US14016444
申请日：2013-09-03
申请人： Sinopower Semiconductor, Inc.
发明人： Po-Hsien Li
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A trench power device includes a semiconductor layer, a trench gate structure, a trench source structure, and a contact. The semiconductor layer has an epitaxial layer, a doped body region, a S/D region, and a doped contact-carrying region. The doped body region is formed in the epitaxial layer, the S/D region is formed in the doped body region, and the doped contact-carrying region is formed in the doped body region and outside a projecting portion defined by orthogonally projecting from the S/D region to the doped body region. The trench gate structure is embedded in the S/D region, the doped body region, and the epitaxial layer. The trench source structure is embedded in the doped body region and the epitaxial layer, and is connected to the doped contact-carrying region. The contact is connected to the S/D region and the doped contact-carrying region.
摘要翻译：沟槽功率器件包括半导体层，沟槽栅极结构，沟槽源结构和接触。半导体层具有外延层，掺杂体区，S / D区和掺杂接触区。掺杂体区域形成在外延层中，S / D区形成在掺杂体区域中，并且掺杂的接触区形成在掺杂体区域中，并且在从S的正交突出部限定的突出部分的外侧形成 / D区域。沟槽栅极结构嵌入在S / D区域，掺杂体区域和外延层中。沟槽源结构嵌入在掺杂体区域和外延层中，并连接到掺杂的接触区域。该触点连接到S / D区和掺杂的接触区。

5. 发明授权

US08536646B2 Trench type power transistor device 有权
标题翻译：沟槽型功率晶体管器件
公开(公告)号：US08536646B2
公开(公告)日：2013-09-17
申请号：US13237940
申请日：2011-09-21
申请人： Teng-Hao Yeh , Shian-Hau Liao , Chia-Hui Chen , Sung-Shan Tai
发明人： Teng-Hao Yeh , Shian-Hau Liao , Chia-Hui Chen , Sung-Shan Tai
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate.
摘要翻译：本发明提供了包括半导体衬底，至少一个晶体管单元，栅极金属层，源极金属层和第二栅极导电层的沟槽型功率晶体管器件。半导体衬底具有至少一个沟槽。晶体管单元包括设置在沟槽中的第一栅极导电层。栅极金属层和源极金属层设置在半导体衬底上。第二栅极导电层设置在第一栅极导电层和源极金属层之间。第二栅极导电层将第一栅极导电层电连接到栅极金属层，并且第二栅极导电层与源极金属层和半导体衬底电绝缘。

6. 发明授权

US08426914B2 Semiconductor device integrated with converter and package structure thereof 有权
标题翻译：集成转换器的半导体器件及其封装结构
公开(公告)号：US08426914B2
公开(公告)日：2013-04-23
申请号：US13013832
申请日：2011-01-26
申请人： Wei-Chieh Lin
发明人： Wei-Chieh Lin
IPC分类号： H01L29/00
CPC分类号： H01L23/49562 , H01L21/823418 , H01L21/823456 , H01L21/823487 , H01L23/3107 , H01L23/4952 , H01L23/49524 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/088 , H01L29/0649 , H01L29/1087 , H01L29/4175 , H01L29/41766 , H01L29/7813 , H01L29/7835 , H01L2224/0603 , H01L2224/06051 , H01L2224/37147 , H01L2224/40247 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49175 , H01L2224/73221 , H01L2224/8385 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01079 , H01L2924/12032 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012
摘要： The present invention provides a semiconductor device including a semiconductor substrate having a first conductive type, at least one high-side transistor device and at least one low-side transistor device. The high-side transistor device includes a doped high-side base region having a second conductive type, a doped high-side source region having the first conductive type and a doped drain region having the first conductive type. The doped high-side base region is disposed within the semiconductor substrate, and the doped high-side source region and the doped drain region are disposed within the doped high-side base region. The doped high-side source region is electrically connected to the semiconductor substrate, and the semiconductor substrate is regarded as a drain of the low-side transistor device.
摘要翻译：本发明提供一种半导体器件，其包括具有第一导电类型的半导体衬底，至少一个高侧晶体管器件和至少一个低侧晶体管器件。高侧晶体管器件包括具有第二导电类型的掺杂高侧基极区域，具有第一导电类型的掺杂高侧源极区域和具有第一导电类型的掺杂漏极区域。掺杂的高侧基极区域设置在半导体衬底内，并且掺杂的高侧源极区域和掺杂漏极区域设置在掺杂的高侧基极区域内。掺杂的高侧源极区域与半导体衬底电连接，半导体衬底被认为是低侧晶体管器件的漏极。

7. 发明申请

US20130001699A1 TRENCH JUNCTION BARRIER SCHOTTKY STRUCTURE WITH ENHANCED CONTACT AREA INTEGRATED WITH A MOSFET 审中-公开
标题翻译：具有与MOSFET集成的增强接触区的TRENCH JUNCTION BARRIER SCHOTTKY STRUCTURE WITH ENHANCED CONTACT AREA
公开(公告)号：US20130001699A1
公开(公告)日：2013-01-03
申请号：US13171475
申请日：2011-06-29
申请人： Sung-Shan Tai , Po-Hsien Li , Guo-Liang Yang , Shian Hau Liao
发明人： Sung-Shan Tai , Po-Hsien Li , Guo-Liang Yang , Shian Hau Liao
IPC分类号： H01L27/06 , H01L21/283
CPC分类号： H01L29/7813 , H01L27/0629 , H01L29/0623 , H01L29/1095 , H01L29/41708 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/66727 , H01L29/66734 , H01L29/782 , H01L29/872
摘要： An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between the Schottky Barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode.The present invention also discloses that a plurality of trenches with adjacent top mesas can be used to form a Schottky diode with even larger contact area, wherein the trenches are built using the isolation area between two cells of MOSFET with minimum extra overhead by shrinking the dimension of pitch between two trenches.
摘要翻译：本发明的目的是提供一种肖特基二极管结构，以增加肖特基势垒金属与半导体衬底之间的肖特基结的接触面积。肖特基结的接触面积越大，肖特基二极管的正向压降越低，从而提高肖特基二极管的性能和效率。本发明还公开了具有相邻顶部台面的多个沟槽可用于形成具有甚至更大接触面积的肖特基二极管，其中使用MOSFET的两个单元之间的隔离区域构建沟槽，并以最小的额外开销来缩小尺寸在两个沟槽之间的间距。

8. 发明授权

US09799743B1 Trenched power semiconductor element 有权
公开(公告)号：US09799743B1
公开(公告)日：2017-10-24
申请号：US15358182
申请日：2016-11-22
申请人： SINOPOWER SEMICONDUCTOR, INC.
发明人： Po-Hsien Li , Guo-Liang Yang , Wei-Chieh Lin , Jia-Fu Lin
IPC分类号： H01L29/423 , H01L29/40 , H01L21/28 , H01L21/02 , H01L29/51 , H01L29/872 , H01L29/78
CPC分类号： H01L29/4236 , H01L21/02244 , H01L21/02255 , H01L21/28273 , H01L29/408 , H01L29/42336 , H01L29/513 , H01L29/515 , H01L29/7827 , H01L29/8725
摘要： A trenched power semiconductor element, a trenched-gate structure thereof being in an element trench of an epitaxial layer and including at least a shielding electrode, a shielding dielectric layer, a gate electrode, an insulating separation layer, and a gate insulating layer. The shielding electrode is disposed at the bottom of the element trench, the shielding dielectric layer is disposed at a lower portion of the element trench, surrounding the shielding electrode to separate the shielding electrode from the epitaxial layer, wherein the top portion of the shielding dielectric layer includes a hole. The gate electrode is disposed above the shielding electrode, being separated from the hole at a predetermined distance through the insulating separation layer. The insulating separation layer is disposed between the shielding dielectric layer and the gate electrode layer to seal the hole.

9. 发明授权

US08709895B2 Manufacturing method power semiconductor device 有权
标题翻译：制造方法功率半导体器件
公开(公告)号：US08709895B2
公开(公告)日：2014-04-29
申请号：US13038346
申请日：2011-03-01
申请人： Sung-Shan Tai , Hung-Sheng Tsai
发明人： Sung-Shan Tai , Hung-Sheng Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/41766 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a termination structure of a power semiconductor device and a manufacturing method thereof. The power semiconductor device has an active region and a termination region. The termination region surrounds the active region, and the termination structure is disposed in the termination region. The termination structure includes a semiconductor substrate, an insulating layer and a metal layer. The semiconductor substrate has a trench disposed in the termination region. The insulating layer is partially filled into the trench and covers the semiconductor substrate, and a top surface of the insulating layer has a hole. The metal layer is disposed on the insulating layer, and is filled into the hole.
摘要翻译：本发明提供一种功率半导体器件的端接结构及其制造方法。功率半导体器件具有有源区和端接区。终端区域围绕有源区域，终端结构设置在终端区域中。端接结构包括半导体衬底，绝缘层和金属层。半导体衬底具有设置在终端区域中的沟槽。绝缘层部分地填充到沟槽中并且覆盖半导体衬底，并且绝缘层的顶表面具有孔。金属层设置在绝缘层上，并被填充到孔中。

10. 发明授权

US08441067B2 Power device with low parasitic transistor and method of making the same 有权
标题翻译：具有低寄生晶体管的功率器件及其制造方法
公开(公告)号：US08441067B2
公开(公告)日：2013-05-14
申请号：US13070479
申请日：2011-03-24
申请人： Wei-Chieh Lin
发明人： Wei-Chieh Lin
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0869 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： The power device with low parasitic transistor comprises a recessed transistor and a heavily doped region at a side of a source region of the recessed transistor. The conductive type of the heavily doped region is different from that of the source region. In addition, a contact plug contacts the heavily doped region and connects the heavily doped region electrically. A source wire covers and contacts the source region and the contact plug to make the source region and the heavily doped region have the same electrical potential.
摘要翻译：具有低寄生晶体管的功率器件包括凹陷晶体管和位于凹陷晶体管的源极区一侧的重掺杂区域。重掺杂区域的导电类型与源极区域的导电类型不同。此外，接触插塞接触重掺杂区域并电连接重掺杂区域。源极线覆盖并接触源极区域和接触插塞以使源极区域和重掺杂区域具有相同的电势。

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